Texas Instruments CD74HCT86M96, CD74HCT86M, CD74HCT86E, CD74HC86M96, CD74HC86M Datasheet
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[ /Title (CD74 HC86, CD74 HCT86
)
/Subject (High Speed CMOS Logic Quad 2-Input EXCL USIVE OR
|
CD74HC86, |
Data sheet acquired from Harris Semiconductor |
CD74HCT86 |
SCHS137 |
|
|
High Speed CMOS Logic |
August 1997 |
Quad 2-Input EXCLUSIVE OR Gate |
Features
•Typical Propagation Delay: 9ns at VCC = 5V, CL = 15pF, TA = 25oC
•Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
Description
The Harris CD74HC86, CD74HCT86 contain four independent EXCLUSIVE OR gates in one package. They provide the system designer with a means for implementation of the EXCLUSIVE OR function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH
Applications
•Logical Comparators
•Parity Generators and Checkers
•Adders and Subtractors
Ordering Information
|
TEMP. RANGE |
|
PKG. |
PART NUMBER |
(oC) |
PACKAGE |
NO. |
CD74HC86E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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|
|
|
CD74HCT86E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
|
|
|
|
CD74HC86M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
|
|
|
|
CD74HCT86M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
|
|
|
|
CD54HC86W |
-55 to 125 |
Wafer |
|
|
|
|
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CD54HCT86W |
-55 to 125 |
Wafer |
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|
|
|
|
CD54HC86H |
-55 to 125 |
Die |
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|
|
|
|
NOTE: When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
1A |
1 |
|
14 |
VCC |
1B |
|
|
|
4B |
2 |
|
13 |
||
1Y |
|
|
|
4A |
3 |
|
12 |
||
2A |
|
|
|
4Y |
4 |
|
11 |
||
2B |
|
|
|
3B |
5 |
|
10 |
||
2Y |
|
|
|
3A |
6 |
|
9 |
||
GND |
|
|
|
3Y |
7 |
|
8 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1644.1 |
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Copyright © Harris Corporation 1997 |
1 |
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CD74HC86, CD74HCT86
Functional Diagram
|
1 |
14 |
|
1A |
VCC |
|
2 |
13 |
|
1B |
4B |
|
3 |
12 |
|
1Y |
4A |
|
4 |
11 |
|
2A |
4Y |
|
5 |
10 |
|
2B |
3B |
|
6 |
9 |
|
2Y |
3A |
|
7 |
8 |
|
GND |
3Y |
|
TRUTH TABLE |
|
|
INPUTS |
OUTPUT |
nA |
nB |
nY |
L |
L |
L |
L |
H |
H |
H |
L |
H |
H |
H |
L |
NOTE: H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
nB
2
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