CY54/74FCT646T
SCCS031 - July 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature permits live insertion
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current 64 mA (Com’l), 48 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
• Independent register for A and B buses
• Extended commercial range of −40˚C to +85˚C
Functional Description
The FCT646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexedtransmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control
G and direction pins are
provided to control the transceiver function. In the transceiver
mode, data present at the high-impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the enable control
G is Active LOW. In the isolation mode
(enable Control
G HIGH), A data may be stored in the B reg-
ister and/or B data may be stored in the A register.
The outputs of the FCT646T are designed with a power-off
disable feature to allo w for liv e insertion of boards.
Logic Block Diagram
Pin Configurations
C
D
B
1
28
4
5678910
3
2
1
27
13
14
15
16
17
26
2524232221
20
11
12
19
A
3
A
5
A
4
B
2
B
5
18
B
1
NC
NC
B
4
A
2
LCC
Top View
B
3
C
D
A
1
TO 7 OTHER CHANNELS
SAB
CPAB
CPBA
DIR
SBA
G
V
CC
CPAB
A
7
A
8
B
6
B
7
B
8
CPBA
SAB
SBA
DIR
A
6
A
1
G
NC
NC
GND
Function Block Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
15
QSOP, SOIC
Top View
CPAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
CPBA
SAB
SBADIR
G
GND
CPAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
CPBA
SAB
SBA
DIR
G
Pin Description
Name Description
A Data Register A Inputs, Data Register B Outputs
B Data Register B Inputs, Data Register A Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
DIR, G Output Enable Inputs