Texas Instruments CY74FCT163373CPVCT, CY74FCT163373CPVC, CY74FCT163373CPACT, CY74FCT163373CPAC Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

CY74FCT163373

SCCS053 - March 1997 - Revised March 2000

16-Bit Latch

Features

•Low power, pin-compatible replacement for LCX and LPT families

•5V tolerant inputs and outputs

•24 mA balanced drive outputs

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for reduced noise

•FCT-C speed at 4.2 ns

•Latch-up performance exceeds JEDEC standard no. 17

•Typical output skew < 250 ps

•Industrial temperature range of –40˚C to +85˚C

•TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

•TypicalVolp (ground bounce) performance exceeds Mil Std 883D

•VCC = 2.7V to 3.6V

•ESD (HBM) > 2000V

Functional Description

This device is a 16-bit, D-type latch, designed for use in bus applications requiring high speed and low power. It can either be used as two independent 8-bit latches, or as a single 16-bit latch by connecting the Output Enable (OE) and Latch (LE) inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce. Flow-through pinout and small shrink packaging aid in simplifying board layout.

The CY74FCT163373 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion.

Logic Block Diagrams CY74FCT163373																Pin Configuration
																				SSOP/TSSOP
																				Top View
1	OE																		1		48
																1OE							1LE
1LE																1O1			2		47		1D1
																1O2			3		46		1D2
																GND			4		45		GND
1D1									D
															1O1	1O3			5		44		1D3
									C							1O4			6		43		1D4
																VCC			7		42		VCC
																1O5			8		41		1D5
																1O6			9		40		1D6
						TO 7 OTHER CHANNELS										GND			10		39		GND
																1O7			11		38		1D7
																1O8			12		37		1D8
																2O1				13	36		2D1
	2OE																			14	35
																2O2							2D2
																GND				15	34		GND
	2LE															2O3				16	33		2D3
																				17	32
	2D1									D						2O4							2D4
																				18	31
															2O1	VCC							VCC
										C						2O5				19	30		2D5
																2O6				20	29		2D6
																GND				21	28		GND
																2O7				22	27		2D7
						TO 7 OTHER CHANNELS										2O8				23	26		2D8
																2							2LE
																	OE			24	25

Copyright © 2000, Texas Instruments Incorporated

CY74FCT163373

Pin Description

	Name		Description
	D		Data Inputs
	LE		Latch Enable Inputs (Active HIGH)
			Output Enable Inputs (Active LOW)
	OE
	O		Three-State Outputs

Maximum Ratings[2, 3]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ......................................	−55°C to +125°C
Ambient Temperature with	−55°C to +125°C
Power Applied ..................................................
Supply Voltage Range .....................................	0.5V to +4.6V
DC Input Voltage .................................................	−0.5V to +7.0V

Function Table[1]

	Inputs				Outputs
D	LE				O
			OE
H	H		L		H
L	H		L		L
X	L		L		Q0
X	X		H		Z

DC Output Voltage ..............................................	−0.5V to +7.0V
DC Output Current	−60 to +120 mA
(Maximum Sink Current/Pin) ...........................
Power Dissipation ..........................................................	1.0W

Operating Range

	Ambient
Range	Temperature	VCC
Industrial	−40°C to +85°C	2.7V to 3.6V

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

	Parameter	Description			Test Conditions			Min.	Typ.[4]	Max.	Unit
VIH		Input HIGH Voltage	All Inputs					2.0		5.5	V
VIL		Input LOW Voltage								0.8	V
VH		Input Hysteresis[5]							100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=–18 mA						–0.7	–1.2	V
IIH		Input HIGH Current	VCC=Max., VI=5.5							±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND							±1	µA
IOZH		High Impedance Output Current	VCC=Max., VOUT=5.5V							±1	µA
		(Three-State Output pins)
IOZL		High Impedance Output Current	VCC=Max., VOUT=GND							±1	µA
		(Three-State Output pins)
I	OS	Short Circuit Current[6]	V	CC	=Max., V	=GND		–60	–135	–240	mA
					OUT
IOFF		Power-Off Disable	VCC=0V, VOUT≤4.5V							±100	µA
ICC		Quiescent Power Supply Current	VIN≤0.2V,				VCC=Max.		0.1	10	µA
			VIN>VCC–0.2V
	ICC	Quiescent Power Supply Current	VIN=VCC–0.6V[7]				VCC=Max.		2.0	30	µA
		(TTL inputs HIGH)
Note:

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop.

2.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.

3.With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

4.Typical values are at VCC=3.3V, TA = +25˚C ambient.

5.This parameter is specified but not tested.

6.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

7.Per TTL driven input; all other inputs at VCC or GND.

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