Texas Instruments CY74FCT652TQCT, CY74FCT652TQC, CY74FCT652CTSOCT, CY74FCT652CTSOC, CY74FCT652CTQCT Datasheet

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Texas Instruments CY74FCT652TQCT, CY74FCT652TQC, CY74FCT652CTSOCT, CY74FCT652CTSOC, CY74FCT652CTQCT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT652T

SCCS032 - September 1994 - Revised March 2000

8-Bit Registered Transceiver

Features

•Function, pinout, and drive compatible with FCT and F logic

•FCT-C speed at 5.4 ns max. (Com’l)

FCT-A speed at 6.3 ns max. (Com’l)

• Reduced V (typically = 3.3V) versions of equivalent

FCT functions

•Edge-rate control circuitry for signiﬁcantly improved noise characteristics

•Power-off disable feature

•Matched rise and fall times

•Fully compatible with TTL input and output logic levels

• Sink Current	64 mA
Source Current	32 mA

•Independent register for A and B buses

•Multiplexed real-time and stored data transfer

•Extended commercial range of−40˚C to +85˚C

Functional Description

The FCT652T consists of bus transceiver circuits, D-type ﬂip-ﬂops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data.

Data on the A or B data bus, or both, can be stored in the internal D ﬂip-ﬂops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type ﬂip-ﬂops by simultaneously enabling GAB and GBA. In this conﬁguration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

The outputs are designed with a power-off disable feature to allow for live insertion of boards.

Logic Block Diagram		Pin Configurations
CPBA					LCC
					LCC
GAB				Top View
SBA			6	5	4	NC	3 2 1
SBA			A	A	A	NC	A A A
SAB			11 10 9			8	7	6	5
		A7	12						4	GAB
GBA		A8	13						3	SAB
CPAB		GND	14						2	CPAB
CPAB		NC	15						1	NC
	B REG	B8	16						28	VCC
	B REG	B7	17						27	CPBA
		B7	17						27	CPBA
		B6	18						26	SBA
1 OF 8 CHANNELS		B6	18							SBA
1 OF 8 CHANNELS	D		19 20 21 22 2324 25
	D
			5	4 3		NC	2 1		GBA
	C		B	B	B	NC	B B		GBA
A1				SOIC/QSOP
					Top View
A REG		B1
		B1	CPAB	1					24	VCC
			CPAB	1					24	VCC
D			SAB	2					23	CPBA
C			GAB	3					22	SBA
C			A1	4					21	GBA
			A1	4					21	GBA
			A2	5					20	B1
			A3	6					19	B2
			A4	7					18	B3
			A5	8					17	B4
			A6	9					16	B5
			A7	10					15	B6
			A8	11					14	B7
	TO 7 OTHER CHANNELS		GND	12					13	B8
			GND	12					13	B8

CY74FCT652T

BUS A

BUS B

BUS A

BUS B

GAB

GBA

CPAB

CPBA

SAB

SBA

GBA

CPAB

CPBA

SAB

SBA

Real-Time Transfer

Bus B to Bus A

Bus A to Bus B

BUS A

BUS B

BUS A

BUS B

GAB

GBA

CPAB

CPBA

SAB

SBA

GBA

CPAB

CPBA

SAB

SBA

H or L

Transferred Stored Data

Store Data from A and/or B

to A and/or B

Function Table[1]

Inputs

Data I/O

GAB

CPAB

CPBA

SAB

SBA

A1 thru A8

B1 thru B8

Operation or Function

GBA

H or L

Input

Isolation

Store A and B Data

H or L

Input

Unspeciﬁed[2]

Store A, Hold B

X[1]

Input

Output

Store A in both registers

H or L

Unspeciﬁed[2]

Input

Hold A, Store B

X[1]

Output

Input

Store B in both registers

Output

Input

Real-Time B Data to A Bus

H or L

Stored B Data to A Bus

Input

Output

Real-Time A Data to B Bus

H or L

Stored A Data to B Bus

H or L

Output

Stored A Data to B Bus

and Stored B Data to A Bus

Notes:

1.Select control=L: clocks can occur simultaneously. Select control=H: clocks must be staggered in order to load both registers. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition.

2.The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

CY74FCT652T

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................	–65°C to +150°C
Ambient Temperature with	–65°C to +135°C
Power Applied .............................................	–65°C to +135°C
Supply Voltage to Ground Potential ...............	–0.5V to +7.0V
DC Input Voltage............................................	–0.5V to +7.0V
DC Output Voltage .........................................	–0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......	120 mA
Power Dissipation ..........................................................	0.5W
Static Discharge Voltage............................................	>2001V

(per MIL-STD-883, Method 3015)

Operating Range

		Ambient
Range	Range	Temperature	VCC
Commercial	T, AT, CT	–40°C to +85°C	5V ± 5%

Electrical Characteristics Over the Operating Range

	Parameter	Description		Test Conditions			Min.	Typ.[5]	Max.	Unit
VOH		Output HIGH Voltage	VCC=Min., IOH=–32 mA				2.0			V
			VCC=Min., IOH=–15 mA				2.4	3.3		V
VOL		Output LOW Voltage	VCC=Min., IOL=64 mA					0.3	0.55	V
VIH		Input HIGH Voltage					2.0			V
VIL		Input LOW Voltage							0.8	V
VH		Hysteresis[6]	All inputs					0.2		V
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=–18 mA					–0.7	–1.2	V
II		Input HIGH Current	VCC=Max., VIN=VCC						5	A
I	IH	Input HIGH Current[6]	V	=Max., V	IN	=2.7V			±1	A
	IH		CC		IN
I	IL	Input LOW Current[6]	V	=Max., V	IN	=0.5V			±1	A
	IL		CC		IN
IOZH		Off State HIGH-Level	VCC=Max., VOUT=2.7V						10	A
		Output Current

IOZL		Off State LOW-Level	VCC=Max., VOUT=0.5V						–10	A
		Output Current

I	OS	Output Short Circuit Current[7]	V	=Max., V		=0.0V	–60	–120	–225	mA
	OS		CC	OUT
IOFF		Power-Off Disable	VCC=0V, VOUT=4.5V						±1	A

Capacitance[6]

Parameter	Description	Typ.[5]	Max.	Unit
CIN	Input Capacitance	5	10	pF
COUT	Output Capacitance	9	12	pF
Notes:

3.Unless otherwise noted, these limits are over the operating free-air temperature range.

4.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5.Typical values are at VCC=5.0V, TA=+25˚C ambient.

6.This parameter is speciﬁed but not tested.

7.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

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