Texas Instruments CD74HCT74M96, CD74HCT74M, CD74HCT74E, CD74HC74M96, CD74HC74M Datasheet

Data sheet acquired from Harris Semiconductor SCHS124

January 1998

CD54HC74, CD74HC74, CD74HCT74

Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

[ /Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual D FlipFlop with Set

Features

• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC

•Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

This flip-flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input.

The 74HCT logic family is functionally as well as pin compatible with the standard 74LS logic family.

Ordering Information

	TEMP. RANGE		PKG.
PART NUMBER	(oC)	PACKAGE	NO.
CD54HC74F	-55 to 125	14 Ld CERDIP	F14.3
CD74HC74E	-55 to 125	14 Ld PDIP	E14.3
CD74HCT74E	-55 to 125	14 Ld PDIP	E14.3
CD74HC74M	-55 to 125	14 Ld SOIC	M14.15
CD74HCT74M	-55 to 125	14 Ld SOIC	M14.15
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Pinout

CD54HC74, CD74HC74, CD74HCT74

(PDIP, SOIC, CERDIP)

TOP VIEW

1R			1		14	VCC
1D
			2		13	2R
1CP						2D
			3		12
						2CP
1S			4		11
1Q
			5		10	2S
						2Q
1Q			6		9
GND
			7		8	2Q

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1476.1
Copyright © Harris Corporation 1998	1

CD54HC74, CD74HC74, CD74HCT74

Functional Diagram

1

RESET

2

R

5

Q

DATA

D

3

F/F 1

6

CLOCK

CP

Q

S

4

SET

13

RESET

12

R

9

D

Q

DATA

11

F/F 2

8

CP

CLOCK

Q

S

GND = PIN 7

VCC = PIN 14

10

SET

TRUTH TABLE

INPUTS

OUTPUTS

SET

RESET

CP

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H (Note 3)

H (Note 3)

H

H

−

H

H

L

H

H

−

L

L

H

H

H

L

X

Q0

Q0

NOTE:

H

= High Level (Steady State)

L

= Low Level (Steady State)

X

= Don’t Care

− = Low-to-High Transition

Q0 = the level of Q before the indicated input conditions were established.

3. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.

2

CD54HC74, CD74HC74, CD74HCT74

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±25mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information

Thermal Resistance (Typical, Note 4)	θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .	90		-
SOIC Package . . . . . . . . . . . . . . . . . . .	120		-
CERDIP Package . . . . . . . . . . . . . . . .	130		55
Maximum Junction Temperature (Hermetic Package or Die) . .			. 175oC
Maximum Junction Temperature (Plastic Package) .		. . . . . .	. 150oC
Maximum Storage Temperature Range . .	. . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .		. . . . . . .	300oC

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
				4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
				6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-4	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-5.2	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage		VIL
				4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
				6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			4	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			5.2	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND

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