Texas Instruments CY74FCT16543TPVCT, CY74FCT16543TPVC, CY74FCT16543ETPVCT, CY74FCT16543ETPVC, CY74FCT16543ETPACT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.			CY74FCT16543T
Data sheet modified to remove devices not offered.
			CY74FCT162543T
			CY74FCT162H543T
		16-Bit Latched Transceivers
SCCS059 - August 1994 - Revised March 2000

Features

•FCT-E speed at 3.4 ns

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for significantly improved noise characteristics

•Typical output skew < 250 ps

•ESD > 2000V

•TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages

•Industrial temperature range of−40˚C to +85˚C

•VCC = 5V ± 10%

CY74FCT16543T Features:
• 64 mA sink current, 32 mA source current
• Typical V	(ground bounce) <1.0V at V	CC	= 5V,
OLP

TA = 25˚C

CY74FCT162543T Features:

•Balanced 24 mA output drivers

•Reduced system switching noise

• Typical V	(ground bounce) <0.6V at V	CC	= 5V,
OLP
TA= 25˚C

CY74FCT162H543T Features:

•Bus hold retains last active state

•Eliminates the need for external pull-up or pull-down resistors

Functional Description

The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB) must be LOW in order to enter data from A or to take data from B as indicated in the truth table. With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the three-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs flow-through pinout and small shrink packaging and in simplifying board design. The output buffers are designed with a power-off disable feature to allow live insertion of boards.

The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines.

The CY74FCT162H543T is a 24-mA balanced output part that has “bus hold” on the data inputs. The device retains the input’s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

Copyright © 2000, Texas Instruments Incorporated

CY74FCT16543T

CY74FCT162543T

CY74FCT162H543T

Logic Block Diagrams

Pin Configuration

1OEBA			Top View
1CEBA			SSOP/TSSOP
1LEBA
1OEAB		1OEAB	1	56	1OEBA
		1LEAB	2	55	1LEBA
1CEAB
		1CEAB	3	54	1CEBA
1LEAB
		GND	4	53	GND
C
		1A 1	5	52	1B1
1A1
D	1B1	1A 2	6	51	1B2
		VCC	7	50	VCC
C		1A 3	8	49	1B3
D		1A 4	9	48	1B4
		1A 5	10	47	1B5

	GND	11	46	GND
	1A 6			1B6
TO 7 OTHER CHANNELS		12	45
	1A 7	13	44	1B7
FCT16543T-1
	1A 8	14	43	1B8

	2OEBA		2A 1	15	42	2B1
	2CEBA		2A 2	16	41	2B2
	2LEBA		2A 3	17	40	2B3
	2OEAB		GND	18	39	GND
			2A 4	19	38	2B4
	2CEAB		2A 5	20	37	2B5
	2LEAB		2A 6	21	36	2B6
	C		VCC	22	35	VCC
	2A 1	2B1	2A 7	23	34	2B7
	D
			2A 8	24	33	2B8
	C		GND	25	32	GND
			2CEAB	26	31	2CEBA
	D
			2LEAB	27	30	2LEBA
			2OEAB	28	29	2OEBA

TO 7 OTHER CHANNELS FCT16543T-2

FCT16543T-3

Pin Description

	Name				Description
					A-to-B Output Enable Input (Active LOW)
	OEAB
					B-to-A Output Enable Input (Active LOW)
	OEBA
					A-to-B Enable Input (Active LOW)
	CEAB
					B-to-A Enable Input (Active LOW)
	CEBA
					A-to-B Latch Enable Input (Active LOW)
	LEAB
					B-to-A Latch Enable Input (Active LOW)
	LEBA
	A				A-to-B Data Inputs or B-to-A Three-State Outputs[9]
	B				B-to-A Data Inputs or A-to-B Three-State Outputs[9]

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .....................	Com’l	−55°C to +125°C
Ambient Temperature with		−55°C to +125°C
Power Applied .................................	Com’l
DC Input Voltage .................................................		−0.5V to +7.0V
DC Output Voltage ..............................................		−0.5V to +7.0V
DC Output Current		−60 to +120 mA
(Maximum Sink Current/Pin) ...........................

Function Table[1]

Latch

Output

Inputs

Status

Buffers

A to B

B

CEAB

LEAB

OEAB

H

X

X

Storing

High Z

X

H

X

Storing

X

X

X

H

X

High Z

L

L

L

Transparent

Current A

Inputs

L

H

L

Storing

Previous A

Inputs[2]

Power Dissipation ..........................................................

1.0W

Static Discharge Voltage............................................

>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Ambient

Range

Temperature

VCC

Industrial

−40°C to +85°C

5V ± 10%

2

CY74FCT16543T

CY74FCT162543T

CY74FCT162H543T

Electrical Characteristics Over the Operating Range

Parameter		Description			Test Conditions		Min.	Typ.[5]	Max.	Unit
VIH		Input HIGH Voltage					2.0			V
VIL		Input LOW Voltage							0.8	V
VH		Input Hysteresis[6]						100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=−18 mA					−0.7	−1.2	V
IIH		Input HIGH Current	VCC=Max., VI=VCC						±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND						±1	µA
IOZH		High Impedance Output Cur-	VCC=Max., VOUT=2.7V						±1	µA
		rent (Three-State Output pins)
IOZL		High Impedance Output Cur-	VCC=Max., VOUT=0.5V						±1	µA
		rent (Three-State Output pins)
I	OS	Short Circuit Current[7]	V	CC	=Max., V	=GND	−80	−140	−200	mA
					OUT
I	O	Output Drive Current[7]	V	CC	=Max., V	=2.5V	−50		−180	mA
					OUT
I	OFF	Power-Off Disable	V	CC	=0V, V	≤4.5V[8]			±1	µA
					OUT

Notes:

1.A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.

2.Data prior to LEAB LOW-to-HIGH Transition

H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance.

3.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.

4.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5.Typical values are at VCC= 5.0V, TA= +25˚C ambient.

6.This parameter is specified but not tested.

7.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

8.Tested at +25˚C.

9.On the 74FCT162H543T, these pins have bus hold.

3