Texas Instruments CY74FCT543TSOCT, CY74FCT543TSOC, CY74FCT543TQCT, CY74FCT543TQC, CY74FCT543CTSOCT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

CY54/74FCT543T

SCCS030 - May 1994 - Revised March 2000

8-Bit Latched Registered Transceiver

Features

Functional Description

•Function, pinout, and drive compatible with FCT and F logic

•FCT-C speed at 5.3 ns max. (Com’l) FCT-A speed at 6.5 ns max. (Com’l)

•Reduced VOH (typically = 3.3V) versions of equivalent FCT functions

•Edge-rate control circuitry for significantly improved noise characteristics

•Power-off disable feature

•Matched rise and fall times

•Fully compatible with TTL input and output logic levels

•ESD > 2000V

• Sink current	64 mA (Com’l), 48 mA (Mil)
Source current	32 mA (Com’l), 12 mA (Mil)

•Separation controls for data flow in each direction

•Back to back latches for storage

•Extended commercial range of −40˚C to +85˚C

The FCT543T octal latched transceiver contains two sets of eight D-type latches with separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input must be LOW in order to enter data from A or to take data from B, as indicated in the truth table. With CEAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their output no longer change with the A inputs. With CEAB and OEAB both LOW, the three-stage B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs.

The outputs are designed with a power-off disable feature to allow for live insertion of boards.

Functional Block Diagram			Logic Block Diagram
	Detail A
	D Q	B0
	LE		A0	A1	A2	A3	A4	A5	A6	A7
			CEAB
A0	Q D									OEAB
			CEBA
	LE		LEAB
			LEBA							OEBA
A1		B1	B0	B1	B2	B3	B4	B5	B6	B7
A2		B2
A3		B3
A4	Detail A x 7	B4
A5		B5	Pin Configurations
A6		B6
A7		B7			SOIC/QSOP
OEBA
					Top View
		OEAB
CEBA			LEBA		1		24		VCC
		CEAB	OEBA		2		23		CEBA
LEBA				A0	3		22		B0
		LEAB		A1	4		21		B1
				A2	5		20		B2
				A3	6		19		B3
				A4	7		18		B4
				A5	8		17		B5
				A6	9		16		B6
				A7	10		15		B7
			CEAB		11		14		LEAB
			GND		12		13		OEAB

Copyright © 2000, Texas Instruments Incorporated

CY54/74FCT543T

Pin Description

		Name				Description
						A-to-B Output Enable Input (Active LOW)
		OEAB
						B-to-A Output Enable Input (Active LOW)
	OEBA
						A-to-B Enable Input (Active LOW)
	CEAB
						B-to-A Enable Input (Active LOW)
	CEBA
						A-to-B Latch Enable Input (Active LOW)
	LEAB
						B-to-A Latch Enable Input (Active LOW)
	LEBA
	A					A-to-B Data Inputs or B-to-A Three-State Outputs
	B					B-to-A Data Inputs or A-to-B Three-State Outputs

Function Table[1, 2]

			Inputs						Latch	Outputs
									A-to-B[3]	B
	CEAB			LEAB			OEAB
	H			X			X		Storing	High Z
	X			H			X		Storing	X
	X			X			H		X	High Z
	L			L			L		Transpar-	Current A Inputs
									ent
	L			H			L		Storing	Previous A Inputs

Notes:

Maximum Ratings[4, 5]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................	–65°C to +150°C
Ambient Temperature with	–65°C to +135°C
Power Applied.............................................
Supply Voltage to Ground Potential...............	–0.5V to +7.0V
DC Input Voltage ...........................................	–0.5V to +7.0V
DC Output Voltage.........................................	–0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......		120 mA
Power Dissipation ..........................................................		0.5W
Static Discharge Voltage............................................		>2001V

(per MIL-STD-883, Method 3015)

Operating Range

		Ambient
Range	Range	Temperature	VCC
Commercial	DT	0°C to +70°C	5V ± 5%
Commercial	T, AT, CT	–40°C to +85°C	5V ± 5%
Military[6]	All	–55°C to +125°C	5V ± 10%

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

2.A-to-B data flow shown: B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.

3.Before LEAB LOW-to-HIGH Transition.

4.Unless otherwise noted, these limits are over the operating free-air temperature range.

5.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

6.TA is the “instant on” case temperature.

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CY54/74FCT543T

Electrical Characteristics Over the Operating Range

Parameter		Description			Test Conditions			Min.	Typ.[7]	Max.	Unit
VOH		Output HIGH Voltage	VCC=Min., IOH=–32 mA				Com’l	2.0			V
			VCC=Min., IOH=–15 mA				Com’l	2.4	3.3		V
			VCC=Min., IOH=–12 mA				Mil	2.4	3.3		V
VOL		Output LOW Voltage	VCC=Min., IOL=64 mA				Com’l		0.3	0.55	V
			VCC=Min., IOL=48mA				Mil		0.3	0.55	V
VIH		Input HIGH Voltage						2.0			V
VIL		Input LOW Voltage								0.8	V
VH		Hysteresis[8]	All inputs						0.2		V
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=–18 mA						–0.7	–1.2	V
IIH		Input HIGH Current	VCC=Max., VIN=VCC							5	A
I	IH	Input HIGH Current[8]	V	=Max., V	IN	=2.7V				±1	A
			CC
I	IL	Input LOW Current[8]	V	=Max., V	IN	=0.5V				±1	A
			CC
IOZH		Off State HIGH-Level Output	VCC=Max., VOUT = 2.7V							10	A
		Current
IOZL		Off State LOW-Level	VCC= Max., VOUT = 0.5V							–10	A
		Output Current
I	OS	Output Short Circuit Current[9]	V	=Max., V		=0.0V		–60	–120	–225	mA
			CC	OUT
IOFF		Power-Off Disable	VCC=0V, VOUT=4.5V							±1	A

Capacitance[8]

Parameter	Description	Typ.[7]	Max.	Unit
CIN	Input Capacitance	5	10	pF
COUT	Output Capacitance	9	12	pF
Notes:

7.Typical values are at VCC=5.0V, TA=+25˚C ambient.

8.This parameter is specified but not tested.

9.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

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