Texas Instruments CD74HCT564M, CD74HCT564E, CD74HCT534E, CD74HC534E, CD74HC564M Datasheet

Data sheet acquired from Harris Semiconductor SCHS188

January 1998

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered

Features

Description

•

Buffered Inputs

The Harris CD74HC534, CD74HCT534, CD74HC564 and

[ /Title

•

Common Three-State Output-Enable Control

CD74HCT564 are high speed Octal D-Type Flip-Flops manu-

factured with silicon gate CMOS technology. They possess

(CD74

•

Three-State Outputs

the low power consumption of standard CMOS integrated cir-

HC534

•

Bus Line Driving Capability

cuits, as well as the ability to drive 15 LSTTL loads. Due to the

,

large output drive capability and the three-state feature, these

•

Typical Propagation Delay = 13ns at V

= 5V,

devices are ideally suited for interfacing with bus lines in a bus

CD74

CC

CL = 15pF, TA = 25oC (Clock to Output)

organized system. The two types are functionally identical and

HCT53

•

Fanout (Over Temperature Range)

differ only in their pinout arrangements.

4,

The

CD74HC534,

CD74HCT534,

CD74HC564

and

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

CD74

CD74HCT564 are positive edge triggered flip-flops. Data at

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

HC564

the D inputs, meeting the setup and hold time requirements,

• Wide Operating Temperature Range . . . -55oC to 125oC

are inverted and transferred to the Q outputs on the positive

,

•

Balanced Propagation Delay and Transition Times

going transition of the CLOCK input. When a high logic level is

CD74

applied to the OUTPUT ENABLE input, all outputs go to a

HCT56

•

Significant Power Reduction Compared to LSTTL

high impedance state, regardless of what signals are present

Logic ICs

at the other inputs and the state of the storage elements.

• HC Types

The

CD74HCT logic

family is speed, function,

and

pin

compatible with the standard 74LS logic family.

- 2V to 6V Operation

Ordering Information

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

TEMP. RANGE (oC)

PKG.

• HCT Types

PART NUMBER

PACKAGE

NO.

- 4.5V to 5.5V Operation

CD74HC534E

-55 to 125

20 Ld PDIP

E20.3

- Direct LSTTL Input Logic Compatibility,

CD74HCT534E

-55 to 125

20 Ld PDIP

E20.3

VIL= 0.8V (Max), VIH = 2V (Min)

CD74HC564E

-55 to 125

20 Ld PDIP

E20.3

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

CD74HCT564E

-55 to 125

20 Ld PDIP

E20.3

CD74HC564M

-55 to 125

20 Ld SOIC

M20.3

CD74HCT564M

-55 to 125

20 Ld SOIC

M20.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

Pinouts

CD74HC534, CD74HCT534 (PDIP)

CD74HC564, CD74HCT564

(PDIP, SOIC)

TOP VIEW

TOP VIEW

OE	1	20	VCC	OE	1	20	VCC
Q0	2	19	Q7	D0	2	19	Q0

D0

3

18 D7

D1

3

18 Q1

D1

4

17 D6

D2

4

17 Q2

Q1

5

16 Q6

D3

5

16 Q3

Q2

6

15 Q5

D4

6

15 Q4

D2

7

14 D5

D5

7

14 Q5

D3

8

13 D4

D6

8

13 Q6

Q3

9

12 Q4

D7

9

12 Q7

GND

10

11 CP

GND

10

11 CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1640.1

Copyright © Harris Corporation 1998

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CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Functional Diagram
D0	D1	D2	D3	D4	D5	D6	D7
D Q	D Q	D Q	D Q	D Q	D Q	D Q		D Q
CP	CP	CP	CP	CP	CP	CP		CP
CP
OE
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	O7

TRUTH TABLE

				INPUTS			OUTPUT
				CP		Dn
		OE						Qn
		L		−		H		L
		L		−		L		H
		L		L		X	No Change
		H		X		X		Z
NOTE:
H	= High Level (Steady State)
L	= Low Level (Steady State)
X	= Don’t Care
−	= Transition from Low to High Level
Z	= High Impedance State

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CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±35mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 3)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 120
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS		VCC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or VIL	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-7.8	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or VIL	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			6	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			7.8	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND

3