Texas Instruments CY74FCT16500CTPVCT, CY74FCT16500CTPVC, CY74FCT16500CTPACT, CY74FCT16500CTPAC, CY74FCT162500CTPVC Datasheet

Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.

CY74FCT16500T

CY74FCT162500T

SCCS056 - August 1994 - Revised March 2000

18-Bit Registered Transceivers

Features

•FCT-C speed at 4.6 ns

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for significantly improved noise characteristics

•Typical output skew < 250 ps

•ESD > 2000V

•TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages

•Industrial temperature range of−40˚C to +85˚C

•VCC = 5V ± 10%

CY74FCT16500T Features:
• 64 mA sink current, 32 mA source current
• Typical V	(ground bounce) <1.0V at V	CC	= 5V,
OLP

TA = 25˚C

CY74FCT162500T Features:

•Balanced 24 mA output drivers

•Reduced system switching noise

• Typical V	(ground bounce) <0.6V at V	CC	= 5V,
OLP
TA= 25˚C

Functional Description

These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The output buffers are designed with power-off disable feature that allows live insertion of boards.

The CY74FCT16500T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162500T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162500T is ideal for driving transmission lines.

Logic Block Diagram				Pin Configuration
					SSOP/TSSOP
					Top View
				OEAB	1	56	GND
				LEAB	2	55	CLKAB
				A1	3	54	B1
OEAB				GND	4	53	GND
CLKBA				A2	5	52	B2
				A3	6	51	B3
LEBA				VCC	7	50	VCC
OEBA				A4	8	49	B4
				A5	9	48	B5
CLKAB				A6	10	47	B6
LEAB				GND	11	46	GND
				A7	12	45	B7
	C	C		A8	13	44	B8
				A9	14	43	B9
				B1
A1	D	D		A10	15	42	B
							10
				A11	16	41	B11
				A12	17	40	B12
	C	C		GND	18	39	GND
				A13	19	38	B13
	D	D		A14	20	37	B14
				A15	21	36	B15
				VCC	22	35	VCC
				A16	23	34	B16
	TO 17 OTHER CHANNELS			A17	24	33	B17
			FCT16500-1	GND	25	32	GND
				A18			B18
					26	31
				OEBA	27	30	CLKBA
				LEBA	28	29	GND
					FCT16500-2

Copyright © 2000, Texas Instruments Incorporated

CY74FCT16500T

CY74FCT162500T

Pin Summary

	Name			Description
	OEAB			A-to-B Output Enable Input
				B-to-A Output Enable Input (Active LOW)
	OEBA
	LEAB			A-to-B Latch Enable Input
	LEBA			B-to-A Latch Enable Input
				A-to-B Clock Input (Active LOW)
	CLKAB
				B-to-A Clock Input (Active LOW)
	CLKBA

AA-to-B Data Inputs or B-to-A Three-State Outputs

BB-to-A Data Inputs or A-to-B Three-State Outputs

Function Table[1, 2]

	Inputs						Outputs
OEAB	LEAB					A	B
			CLKAB
L	X		X			X	Z
H	H		X			L	L
H	H		X			H	H
H	L					L	L
H	L					H	H
H	L		H			X	B[3]
H	L		L			X	B[4]

Electrical Characteristics Over the Operating Range

Maximum Ratings[5, 6]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .......................	Com’l −55°C to +125°C
Ambient Temperature with	Com’l −55°C to +125°C
Power Applied...................................
DC Input Voltage .................................................	−0.5V to +7.0V
DC Output Voltage ..............................................	−0.5V to +7.0V
DC Output Current	−60 to +120 mA
(Maximum Sink Current/Pin) ...........................
Power Dissipation ..........................................................	1.0W
Static Discharge Voltage............................................	>2001V

(per MIL-STD-883, Method 3015)

Operating Range

	Ambient
Range	Temperature	VCC
Industrial	−40°C to +85°C	5V ± 10%

Parameter		Description			Test Conditions		Min.	Typ.[7]	Max.	Unit
VIH		Input HIGH Voltage					2.0			V
VIL		Input LOW Voltage							0.8	V
VH		Input Hysteresis[8]						100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=−18 mA					−0.7	−1.2	V
IIH		Input HIGH Current	VCC=Max., VI=VCC						±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND.						±1	µA
IOZH		High Impedance Output Current	VCC=Max., VOUT=2.7V						±1	µA
		(Three-State Output pins)
IOZL		High Impedance Output Current	VCC=Max., VOUT=0.5V						±1	µA
		(Three-State Output pins)
I	OS	Short Circuit Current[9]	V	=Max., V		=GND	−80	−140	−200	mA
				CC	OUT
I	O	Output Drive Current[9]	V	=Max., V		=2.5V	−50		−180	mA
				CC	OUT
I	OFF	Power-Off Disable	V	=0V, V		≤4.5V[10]			±1	µA
				CC	OUT

Notes:

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition.

2.A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.

3.Output level before the indicated steady-state input conditions were established.

4.Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.

5.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.

6.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

7.Typical values are at VCC= 5.0V, TA= +25˚C ambient.

8.This parameter is specified but not tested.

9.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

10. Tested at +25˚C.

2