Texas Instruments CY74FCT163H952CPVC, CY74FCT163H952CPAC, CY74FCT163952CPVCT, CY74FCT163952CPVC, CY74FCT163952CPACT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.

CY74FCT163952

CY74FCT163H952

SCCS048 - March 1997 - Revised March 2000

16-Bit Registered Transceivers

Features

Functional Description

•Low power, pin-compatible replacement for LCX and LPT families

•5V tolerant inputs and outputs

•24 mA balanced drive outputs

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for reduced noise

•FCT-C speed at 4.4 ns

•Latch-up performance exceeds JEDEC standard no. 17

•Typical output skew < 250 ps

•Industrial temperature range of –40˚C to +85˚C

•TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

•TypicalVolp (ground bounce) performance exceeds Mil Std 883D

•VCC = 2.7V to 3.6V

•ESD (HBM) > 2000V

CY74FCT163H952

•Bus hold on data inputs

•Eliminates the need for external pull-up or pull-down resistors

•Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels

These 16-bit registered transceivers are high-speed, low-power devices. 16-bit operation is achieved by connecting the control lines of the two 8-bit registered transceivers together. For data flow from bus A-to-B, CEAB must be LOW to allow data to be stored when CLKAB transitions from LOW-to-HIGH. The stored data will be present on the output when OEAB is LOW. Control of data from B-to-A is similar and is controlled by using the CEBA, CLKBA, and OEBA inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce.

The CY74FCT163H952 has “bus hold” on the data inputs, which retains the input’s last state whenever the source driving the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

The CY74FCT163952 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion.

Logic Block Diagrams; CY74FCT163952, CY74FCT163H952				Pin Configuration
					SSOP/TSSOP
					Top View
1CEBA		2CEBA		1OEAB	1	56	1OEBA
				1 CLKAB	2	55	1 CLKBA
1 CLKBA		2 CLKBA		1CEAB	3	54	1CEBA
1OEAB		2OEAB		GND	4	53	GND
				1A1	5	52	1B1
1CEAB		2CEAB		1A2	6	51	1B2
1 CLKAB		2 CLKAB		VCC	7	50	VCC
				1A3	8	49	1B3
1OEBA		2OEBA		1A4	9	48	1B4
	C		C	1A5	10	47	1B5
1A1	CE	2A1	CE	GND	11	46	GND
	D	1B1	D	2B1	12	45	1B6
				1A6
	C		C	1A7	13	44	1B7
	CE		CE
				1A8	14	43	1B8
	D		D
				2A1	15	42	2B1
				2A2	16	41	2B2
				2A3	17	40	2B3
	TO7 OTHERCHANNELS		TO7 OTHERCHANNELS	GND	18	39	GND
				2A4	19	38	2B4
				2A5	20	37	2B5
				2A6	21	36	2B6
				VCC	22	35	VCC
				2A7	23	34	2B7
				2A8	24	33	2B8
				GND	25	32	GND
				2CEAB	26	31	2CEBA
				2 CLKAB	27	30	2 CLKBA
				2OEAB	28	29	2OEBA

Copyright © 2000, Texas Instruments Incorporated

CY74FCT163952

CY74FCT163H952

Pin Description

		Name			Description
					A-to-B Output Enable Input (Active LOW)
		OEAB
					B-to-A Output Enable Input (Active LOW)
	OEBA
					A-to-B Clock Enable Input (Active LOW)
	CEAB
					B-to-A Clock Enable Input (Active LOW)
	CEBA
	CLKAB				A-to-B Clock Input
	CLKBA				B-to-A Clock Input
	A				A-to-B Data Inputs or B-to-A Three-State
					Outputs[1]
	B				B-to-A Data Inputs or A-to-B Three-State
					Outputs[1]

Maximum Ratings[5, 6]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ..................................	–55°C to +125°C
Ambient Temperature with	–55°C to +125°C
Power Applied .............................................
Supply Voltage Range......................................	0.5V to +4.6V
DC Input Voltage ............................................	–0.5V to +7.0V
DC Output Voltage .........................................	–0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ........................	–60 to +120 mA
Power Dissipation..........................................................	1.0W

Function Table[2, 3]

For A-to-B (Symmetric with B-to-A)

						Inputs					Outputs
			CLKAB							A	B
	CEAB							OEAB
	H			X				L		X	B[4]
	X			L				L		X	B[4]
	L							L		L	L
	L							L		H	H
	X			X				H		X	Z

Operating Range

	Ambient
Range	Temperature	VCC
Industrial	–40°C to +85°C	2.7V to 3.6V

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

	Parameter	Description			Test Conditions			Min.	Typ.[7]	Max.	Unit
VIH		Input HIGH Voltage	All Inputs					2.0		5.5	V
VIL		Input LOW Voltage								0.8	V
VH		Input Hysteresis[8]							100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=–18 mA						–0.7	–1.2	V
IIH		Input HIGH Current	VCC=Max., VI=5.5							±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND							±1	µA
IOZH		High Impedance Output Current	VCC=Max., VOUT=5.5V							±1	µA
		(Three-State Output pins)
IOZL		High Impedance Output Current	VCC=Max., VOUT=GND							±1	µA
		(Three-State Output pins)
I	OS	Short Circuit Current[9]	V	CC	=Max., V =GND			–60	–135	–240	mA
					OUT
IOFF		Power-Off Disable	VCC=0V, VOUT≤4.5V							±100	µA
ICC		Quiescent Power Supply Current	VIN≤0.2V,				VCC=Max.		0.1	10	µA
			VIN>VCC–0.2V
	ICC	Quiescent Power Supply Current	VIN=VCC–0.6V[10]				VCC=Max.		2.0	30	µA
		(TTL inputs HIGH)
Notes:

1.On the CY74FCT163H952, these pins have bus hold.

2.A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA.

3.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. Z = HIGH Impedance.

4.Level of B before the indicated steady-state input conditions were established.

5.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature.

6.With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground,

7.Typical values are at VCC=3.3V, TA = +25˚C ambient.

8.This parameter is specified but not tested.

9.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

10. Per TTL driven input; all other inputs at VCC or GND.

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