Texas Instruments CD74HCT4060M96, CD74HCT4060M, CD74HCT4060E, CD74HC4060M96, CD74HC4060M Datasheet
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Data sheet acquired from Harris Semiconductor SCHS207
February 1998
CD74HC4060,
CD74HCT4060
High Speed CMOS Logic 14-Stage Binary Counter with Oscillator
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Features |
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Onboard Oscillator |
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[ /Title |
• Common Reset |
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(CD74 |
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Negative Edge Clocking |
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HC406 |
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, |
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0, |
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T = 25oC |
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CD74 |
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A |
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Fanout (Over Temperature Range) |
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HCT40 |
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- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads |
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60)- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
/Sub- |
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Wide Operating Temperature Range . . . -55oC to 125oC |
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ject |
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Balanced Propagation Delay and Transition Times |
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(High |
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Significant Power Reduction Compared to LSTTL |
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Speed |
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CMOS |
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Logic ICs |
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•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
Pinout
CD74HC4060, CD74HCT4060
(PDIP, SOIC)
TOP VIEW
Q12 |
1 |
16 VCC |
Q13 |
2 |
15 |
Q10 |
Q14 |
3 |
14 |
Q8 |
Q6 |
4 |
13 |
Q9 |
Q5 |
5 |
12 |
MR |
Q7 |
6 |
11 |
φI |
Q4 |
7 |
10 |
φO |
GND |
8 |
9 |
φO |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1654.1 |
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Copyright © Harris Corporation 1998
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CD74HC4060, CD74HCT4060
Description
The Harris CD74HC4060 and CD74HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of φI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels.
Ordering Information
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TEMP. RANGE (oC) |
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PKG. |
PART NUMBER |
PACKAGE |
NO. |
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CD74HC4060E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HCT4060E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HC4060M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HCT4060M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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NOTES: |
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1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
Functional Diagram
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7 |
Q4 |
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5 |
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Q5 |
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4 |
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12 |
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Q6 |
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MR |
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6 |
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Q7 |
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14 |
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14-STAGE |
Q8 |
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RIPPLE |
13 |
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11 |
COUNTER |
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φI |
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AND |
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Q9 |
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15 |
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OSCILLATOR |
Q10 |
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1 |
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Q12 |
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2 |
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Q13 |
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3 |
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Q14 |
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9 |
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φO |
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GND = 8 |
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10 |
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VCC = 16 |
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φO |
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2
CD74HC4060, CD74HCT4060
9 |
ø1 |
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ø4 |
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ø5 |
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ø14 Q14 |
øO |
Q1 |
Q4 |
Q13 |
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10 |
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øO |
FF1 |
FF4 |
FF5 - FF13 |
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FF14 |
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11 |
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ø1 |
ø1 |
Q1 |
ø4 |
Q4 |
ø5 |
Q13 |
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ø14 Q14 |
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R |
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R |
R |
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R |
12 |
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MR |
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7 |
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2 |
3 |
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Q4 |
5, 4, 6, 14, 13, 15, 1 |
Q13 |
Q14 |
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Q5 - Q10, Q12 |
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FIGURE 1. LOGIC BLOCK DIAGRAM |
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TRUTH TABLE |
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øI |
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MR |
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OUTPUT STATE |
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− |
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L |
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No Change |
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↓ |
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L |
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Advance to Next State |
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X |
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H |
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All Outputs are Low |
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