Texas Instruments CD74HCT30M96, CD74HCT30M, CD74HCT30E, CD74HC30E, CD74HC30PWR Datasheet

Data sheet acquired from Harris Semiconductor SCHS121

August 1997

CD54HC30, CD74HC30, CD74HCT30

High Speed CMOS Logic

8-Input NAND Gate

[ /Title (CD54H C30, CD74H C30, CD74H CT30) /Subject (High Speed CMOS Logic 8-

Features

•Buffered Inputs

•Typical Propagation Delay: 10ns at VCC = 5V, CL = 15pF, TA = 25oC

•Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The Harris CD74HC30, CD74HCT30, each contain an 8-input NAND gate in one package. They provide the system designer with the direct implementation of the positive logic 8-input NAND function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

Ordering Information

	TEMP. RANGE		PKG.
PART NUMBER	(oC)	PACKAGE	NO.
CD74HC30E	-55 to 125	14 Ld PDIP	E14.3
CD74HCT30E	-55 to 125	14 Ld PDIP	E14.3
CD74HC30M	-55 to 125	14 Ld SOIC	M14.15
CD74HCT30M	-55 to 125	14 Ld SOIC	M14.15
CD54HCT30H	-55 to 125	Die
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Pinout

CD54HC30, CD74HC30, CD74HCT30

(PDIP, CERDIP, SOIC)

TOP VIEW

A	1		14		VCC
B					NC
	2		13
C					H
	3		12
D					G
	4		11
E					NC
	5		10
F					NC
	6		9
GND
	7		8		Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1652.1
Copyright © Harris Corporation 1997	1

CD54HC30, CD74HC30, CD74HCT30

Functional Diagram

	A	1
		2
	B
		3
	C
		4	8
	D
		5
	E		Y
		6
	F
		11	Y = ABCDEFGH
	G	12
	H

TRUTH TABLE

			INPUTS
A	B	C	D	E	F	G	H	OUTPUT
L	X	X	X	X	X	X	X	H
X	L	X	X	X	X	X	X	H
X	X	L	X	X	X	X	X	H
X	X	X	L	X	X	X	X	H
X	X	X	X	L	X	X	X	H
X	X	X	X	X	L	X	X	H
X	X	X	X	X	X	L	X	H
X	X	X	X	X	X	X	L	H
H	H	H	H	H	H	H	H	L

NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant

Logic Symbol

1

A

2

B

3

C

4

D

8

Y

5

E

6

F

11

G

12

H

2