Texas Instruments CY74FCT163H374CPVC, CY74FCT163H374CPAC, CY74FCT163374CPVCT, CY74FCT163374CPVC, CY74FCT163374CPACT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.

CY74FCT163374

CY74FCT163H374

SCCS050 - March 1997 - Revised March 2000

16-Bit Registers

Features

•Low power, pin-compatible replacement for LCX and LPT families

•5V tolerant inputs and outputs

•24 mA balanced drive outputs

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for reduced noise

•FCT-C speed at 5.2 ns

•Latch-up performance exceeds JEDEC standard no. 17

•Typical output skew < 250 ps

•Industrial temperature range of –40˚C to +85˚C

•TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

•Typical V (ground bounce) performance exceeds Mil Std 883Dolp

•VCC = 2.7V to 3.6V

•ESD (HBM) > 2000V

CY74FCT163H374

•Bus hold on data inputs

•Eliminates the need for external pull-up or pull-down resistors

•Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels

Functional Description

These devices are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors, and provide for minimal undershoot and reduced ground bounce. Flow-through pinout and small shrink packaging aid in simplifying board layout.

The CY74FCT163H374 has “bus hold” on the data inputs, which retains the input’s last state whenever the source driving the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

The CY74FCT163374 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion.

Logic Block Diagrams CY74FCT163374, CY74FCT163H374																				Pin Configuration
																								SSOP/TSSOP
																								Top View
																							1
																				1					48		1CLK
																					OE
																				1O1			2		47		1D1
																				1O2			3		46		1D2
1	OE									2	OE									GND			4		45		GND
																				1O3			5		44		1D3
1CLK										2CLK										1O4			6		43		1D4
																				VCC			7		42		VCC
1D1					D					2D1					D					1O5			8		41		1D5
									1O1						C				2O1	1O6			9		40		1D6
					C															GND							GND
																							10		39
																				1O7			11		38		1D7
																				1O8			12		37		1D8
																				2O1				13	36		2D1
			TO 7 OTHER CHANNELS										TO 7 OTHER CHANNELS							2O2				14	35		2D2
																								15	34
																				GND							GND
																				2O3				16	33		2D3
																								17	32
																				2O4							2D4
																								18	31
																				VCC							VCC
																				2O5				19	30		2D5
																				2O6				20	29		2D6
																				GND				21	28		GND
																				2O7				22	27		2D7
																				2O8				23	26		2D8
																				2	OE			24	25		2CLK

Lite Drive is a trademark of Cypress Semiconductor Corporation.

Copyright © 2000, Texas Instruments Incorporated

CY74FCT163374

CY74FCT163H374

Function Table[1]

	Inputs							Outputs
D	CLK							O	Function
						OE
X		L				H		Z	High-Z
X		H				H		Z
L						L		L	Load
									Register
H						L		H
L						H		Z
H						H		Z

Pin Description

	Name		Description
	D		Data Inputs[2]
	CLK		Clock Inputs
			Three-State Output Enable Inputs (Active LOW)
	OE
	O		Three-State Outputs

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .....................................	−55°C to +125°C
Ambient Temperature with	−55°C to +125°C
Power Applied ..................................................
Supply Voltage Range .....................................	0.5V to +4.6V
DC Input Voltage .................................................	−0.5V to +7.0V
DC Output Voltage ..............................................	−0.5V to +7.0V
DC Output Current	−60 to +120 mA
(Maximum Sink Current/Pin) ...........................
Power Dissipation ..........................................................	1.0W

Operating Range

	Ambient
Range	Temperature	VCC
Industrial	−40°C to +85°C	2.7V to 3.6V

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

	Parameter	Description			Test Conditions			Min.	Typ.[5]	Max.	Unit
VIH		Input HIGH Voltage	All Inputs					2.0		5.5	V
VIL		Input LOW Voltage								0.8	V
VH		Input Hysteresis[6]							100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=–18 mA						–0.7	–1.2	V
IIH		Input HIGH Current	VCC=Max., VI=5.5							±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND							±1	µA
IOZH		High Impedance Output Current	VCC=Max., VOUT=5.5V							±1	µA
		(Three-State Output pins)
IOZL		High Impedance Output Current	VCC=Max., VOUT=GND							±1	µA
		(Three-State Output pins)
I	OS	Short Circuit Current[7]	V	CC	=Max., V	=GND		–60	–135	–240	mA
					OUT
IOFF		Power-Off Disable	VCC=0V, VOUT≤4.5V							±100	µA
ICC		Quiescent Power Supply Current	VIN≤0.2V,				VCC=Max.		0.1	10	µA
			VIN>VCC–0.2V
	ICC	Quiescent Power Supply Current	VIN=VCC–0.6V[8]				VCC=Max.		2.0	30	µA
		(TTL inputs HIGH)

Notes:

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = LOW-to-HIGH Transition.

2.On the CY74FCT163H374, these pins have “bus hold.”

3.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.

4.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground

5.Typical values are at VCC=3.3V, TA = +25˚C ambient.

6.This parameter is specified but not tested.

7.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

8.Per TTL driven input; all other inputs at VCC or GND.

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CY74FCT163374

CY74FCT163H374

Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter

Description

Test Conditions

Min.

Typ.[5]

Max.

Unit

VIH

Input HIGH Voltage

All Inputs

2.0

VCC

V

VIL

Input LOW Voltage

0.8

V

VH

Input Hysteresis[6]

100

mV

VIK

Input Clamp Diode Voltage

VCC=Min., IIN=–18 mA

–0.7

– 1.2

V

IIH

Input HIGH Current

VCC=Max., VI=VCC

±100

µA

IIL

Input LOW Current

±100

µA

IBBH

Bus Hold Sustain Current on Bus Hold Input[9]

VCC=Min.

VI=2.0V

–50

µA

IBBL

VI=0.8V

+50

µA

IBHHO

Bus Hold Overdrive Current on Bus Hold In-

VCC=Max., VI=1.5V

±500

µA

IBHLO

put[9]

IOZH

High Impedance Output Current

VCC=Max., VOUT=VCC

±1

µA

(Three-State Output pins)

IOZL

High Impedance Output Current

VCC=Max., VOUT=GND

±1

µA

(Three-State Output pins)

I

OS

Short Circuit Current[7]

V

CC

=Max., V

=GND

–60

–135

–240

mA

OUT

IOFF

Power-Off Disable

VCC=0V, VOUT≤4.5V

±100

µA

ICC

Quiescent Power Supply Current

VIN<0.2V

VCC=Max.

+40

µA

ICC

Quiescent Power supply Current

V

IN

=V

CC

–0.6V[8]

V =Max.

+350

µA

(TTL inputs HIGH)

CC

Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter	Description	Test Conditions	Min.	Typ.[5]	Max.	Unit
IODL	Output LOW Dynamic Current[7]	VCC=3.3V, VIN=VIH	45		110	mA
		or VIL, VOUT=1.5V
IODH	Output HIGH Dynamic Current[7]	VCC=3.3V, VIN=VIH	–45		–110	mA
		or VIL, VOUT=1.5V
VOH	Output HIGH Voltage	VCC=Min., IOH= –0.1 mA	VCC–0.2			V
		VCC=Min., IOH= –8 mA	2.4[10]	3.0		V
		VCC=3.0V, IOH= –24 mA	2.0	3.0		V
VOL	Output LOW Voltage	VCC=Min., IOL= 0.1mA			0.2	V
		VCC=Min., IOL= 24 mA		0.3	0.55
Notes:

9.Pins with bus hold are described in Pin Description.

10. VOH=VCC–0.6V at rated current.

Capacitance[6](T = +25˚C, f = 1.0 MHz)
	A
Parameter	Description	Test Conditions	Typ.[5]	Max.	Unit
CIN	Input Capacitance	VIN = 0V	4.5	6.0	pF
COUT	Output Capacitance	VOUT = 0V	5.5	8.0	pF

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