Texas Instruments CD74HCT4040M96, CD74HCT4040M, CD74HCT4040E, CD74HC4040M96, CD74HC4040M Datasheet
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Data sheet acquired from Harris Semiconductor SCHS203
CD74HC4040,
CD74HCT4040
February 1998
High Speed CMOS Logic
12-Stage Binary Counter
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Features |
at VCC = 5V |
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Fully Static Operation |
• HCT Types |
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- 4.5V to 5.5V Operation |
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Buffered Inputs |
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- Direct LSTTL Input Logic Compatibility, |
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(CD74H |
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Common Reset |
VIL= 0.8V (Max), VIH = 2V (Min) |
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C4040, |
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Negative Edge Pulsing |
- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH |
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CD74HC |
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Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF, |
Description |
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T4040) |
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TA = 25oC |
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/Subject |
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Fanout (Over Temperature Range) |
The Harris CD74HC4040 and CD74HCT4040 are 14-stage |
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(High |
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ripple-carry binary counters. All counter stages are master- |
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Speed |
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- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads |
slave flip-flops. The state of the stage advances one count |
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on the negative clock transition of each input pulse; a high |
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CMOS |
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- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads |
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voltage level on the MR line resets all counters to their zero |
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Wide Operating Temperature Range . . . -55oC to 125oC |
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Logic |
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state. All inputs and outputs are buffered. |
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12-Stage |
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Balanced Propagation Delay and Transition Times |
Ordering Information |
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Binary |
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Significant Power Reduction Compared to LSTTL |
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Logic ICs |
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TEMP. RANGE (oC) |
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PKG. |
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• HC Types |
PART NUMBER |
PACKAGE |
NO. |
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- 2V to 6V Operation |
CD74HC4040E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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- High Noise Immunity: NIL = 30%, NIH = 30% of VCC |
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CD74HCT4040E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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Pinout
CD74HC4040, CD74HCT4040
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(PDIP, SOIC) |
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TOP VIEW |
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Q12 |
1 |
16 |
VCC |
Q6 |
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15 |
Q11 |
Q5 |
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14 |
Q10 |
Q7 |
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13 |
Q8 |
Q4 |
5 |
12 |
Q9 |
Q3 |
6 |
11 |
MR |
Q2 |
7 |
10 |
CP |
GND |
8 |
9 |
Q1‘ |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1483.2 |
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Copyright © Harris Corporation 1998
1
CD74HC4040, CD74HCT4040
Functional Diagram
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VCC |
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10 |
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16 |
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Q1’ |
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INPUT |
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7 |
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Q2 |
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PULSES |
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6 |
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Q3 |
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5 |
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Q4 |
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3 |
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Q5 |
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12-STAGE |
2 |
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Q6 |
BUFFERED |
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RIPPLE |
4 |
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Q7 |
OUTPUTS |
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COUNTER |
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13 |
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Q8 |
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12 |
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Q9 |
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14 |
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Q10 |
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15 |
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Q11 |
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11 |
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1 |
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Q12 |
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MASTER |
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RESET |
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8 |
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GND |
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TRUTH TABLE |
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CP COUNT |
MR |
OUTPUT STATE |
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− |
L |
No Change |
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↓ |
L |
Advance to Next State |
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X |
H |
All Outputs Are Low |
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NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, − = Transition from Low to High Level, ↓ = Transition from High to Low.
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Diagram Logic |
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10 |
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CD74HC4040, |
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CP |
CP |
Q |
CP |
Q |
CP |
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CP |
Q |
CP |
Q |
CP |
Q |
CP |
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CP |
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CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
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I Q’ |
2 |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
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CP |
Q |
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R |
R |
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R |
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R |
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R |
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R |
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R |
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R |
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R |
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R |
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3 |
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MR |
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CD74HCT4040 |
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9 |
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7 |
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6 |
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2 |
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13 |
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Q1’ |
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Q2 |
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Q3 |
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Q4 |
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Q5 |
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Q6 |
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Q7 |
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Q8 |
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Q9 |
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Q10 |
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Q11 |
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Q12 |
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