Texas Instruments CY74FCT480ATPC, CY74FCT480BTSOCT, CY74FCT480BTSOC, CY74FCT480BTQCT, CY74FCT480BTQC Datasheet

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Texas Instruments CY74FCT480ATPC, CY74FCT480BTSOCT, CY74FCT480BTSOC, CY74FCT480BTQCT, CY74FCT480BTQC Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

CY54/74FCT480T

SCCS025 - May 1993 - Revised March 2000

Dual 8-Bit Parity Generator/Checker

Features

Function, pinout and drive compatible with FCT and F logic

FCT-A speed at 7.5 ns max. (Com’l) FCT-B speed at 5.6 ns max. (Com’l)

Reduced VOH (typically = 3.3V) versions of equivalent FCT functions

Edge-rate control circuitry for significantly improved noise characteristics

Power-off disable feature

Matched rise and fall times

ESD > 2000V

Fully compatible with TTL input and output logic levels

• Sink Current

64 mA (Com’l),

 

32 mA (Mil)

Source Current

32 mA (Com’l),

 

12 mA (Mil)

Two 8-bit parity generator/checkers

Open drain Active LOW parity error output

Expandable for larger word widths

Functional Description

The FCT480T is a high-speed dual 8-bit parity generator/checker. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity error output. The FCT480T can be used in ODD parity systems. The parity error output is open-drain, designed for easy expansion of the word width by a wired-OR connection of several FCT480T type devices. Since additional logic is not needed, the parity generation or checking times remain the same as for an individual FCT480T device.

The outputs are designed with a power-off disable feature to allow for live insertion of boards.

Logic Block Diagram

A1

B1

C1

D1

E1

F1

G1

H1

PAR1

CHK/GEN

A2

B2

C2

D2

E2

F2

G2

H2

PAR2

Pin Configurations

LCC

Top View

 

 

 

 

 

 

1

H G

NC F

E

D

 

 

 

 

 

 

 

PAR

 

 

 

 

 

 

 

 

1 1

 

1

1

 

1

 

 

 

 

 

 

 

1110 9

8

7

6

5

 

CHK/GEN

C1

12

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ODD1

 

 

 

 

 

 

B1

 

13

 

 

 

 

 

 

3

 

 

GND

 

 

 

 

 

 

A1

 

 

14

 

 

 

 

 

 

2

 

 

 

NC

 

 

 

 

 

 

NC

 

 

 

15

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ODD2

 

 

 

 

 

 

VCC

 

16

 

 

 

 

 

 

28

 

ERROR

 

17

 

 

 

 

 

 

27

A2

 

 

PAR2

18

 

 

 

 

 

 

26

B2

 

 

 

 

 

 

19 20 21 22 23 24 25

 

 

 

 

 

 

 

2

2

2

 

2 2

2

 

 

 

 

 

 

 

H

G

F

NC E D

 

C

 

FCT480T–2

ODD1

ERR

ODD2

FCT480T–1

DIP/SOIC/QSOP

Top View

 

 

A1

1

24

 

 

VCC

2

23

 

 

 

B1

 

 

A2

3

 

 

 

C1

22

 

 

B2

4

21

 

 

 

D1

 

 

C2

5

20

 

 

 

E1

 

 

D2

6

 

 

 

F1

19

 

 

E2

 

 

 

 

G1

7

18

 

 

F2

 

 

H1

8

 

 

 

17

 

 

G2

 

 

 

PAR1

9

16

 

 

H2

 

 

 

 

 

 

 

 

 

 

 

CHK/GEN

 

10

15

 

 

PAR2

 

ODD

1

11

14

 

 

ERROR

GND

12

13

 

 

 

2

 

 

ODD

FCT480T–3

Copyright © 2000, Texas Instruments Incorporated

CY54/74FCT480T

Function Table

 

Inputs

 

 

 

 

 

 

 

 

Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1 to H1

A2 to H2

CHK/GEN

 

PAR1

PAR2

 

ODD1

ODD2

ERROR

Number of A1 to H1 Inputs

Number of A2 to H2 Inputs

H

H

H

 

L

 

L

 

H

HIGH is EVEN

HIGH is EVEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

L

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

L

X

X

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

Number of Inputs HIGH A2

H

H

H

 

L

 

H

 

L

 

to H2 is ODD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

H

 

H

 

L

 

 

 

 

 

H

L

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

L

X

X

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

Number of A1 to H1 Inputs

Number of A2 to H2 Inputs

H

H

H

 

H

 

L

 

L

HIGH is ODD

HIGH is EVEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

L

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

L

X

X

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

Number of A2 to H2 Inputs

H

H

H

 

H

 

H

 

L

 

HIGH is ODD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

L

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

L

X

X

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum Ratings[1, 2]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................

–65°C to +150°C

Ambient Temperature with

–65°C to +135°C

Power Applied .............................................

Supply Voltage to Ground Potential ...............

–0.5V to +7.0V

DC Input Voltage............................................

–0.5V to +7.0V

DC Output Voltage .........................................

–0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin).......

120 mA

Power Dissipation ..........................................................

 

0.5W

Static Discharge Voltage............................................

>2001V

(per MIL-STD-883, Method 3015)

 

Operating Range

 

 

Ambient

 

Range

Range

Temperature

VCC

Commercial

All

–40°C to +85°C

5V ± 5%

 

 

 

 

Military[3]

All

–55°C to +125°C

5V ± 10%

Notes:

1.Unless otherwise noted, these limits are over the operating free-air temperature range.

2.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

3.TA is the “instant on” case temperature.

2

CY54/74FCT480T

Electrical Characteristics Over the Operating Range

Parameter

Description

 

Test Conditions

 

Min.

Typ.[4]

Max.

Unit

VOH

Output HIGH Voltage

VCC = Min., IOH = –32 mA

Com’l

2.0

 

 

V

 

 

 

VCC = Min., IOH = –15 mA

Com’l

2.4

3.3

 

V

 

 

 

VCC = Min., IOH = –12 mA

Mil

2.4

3.3

 

V

VOL

Output LOW Voltage

VCC = Min., IOL = 64 mA

Com’l

 

0.3

0.55

V

 

 

 

VCC = Min., IOL = 32 mA

Mil

 

0.3

0.55

V

VIH

Input HIGH Voltage

 

 

 

 

2.0

 

 

V

VIL

Input LOW Voltage

 

 

 

 

 

 

0.8

V

VH

Hysteresis[5]

All inputs

 

 

 

0.2

 

V

VIK

Input Clamp Diode Voltage

VCC = Min., IIN = –18 mA

 

 

–0.7

–1.2

V

II

Input HIGH Current

VCC = Max., VIN = VCC

 

 

 

5

A

IIH

Input HIGH Current

VCC = Max., VIN = 2.7V

 

 

 

±1

A

IIL

Input LOW Current

VCC = Max., VIN = 0.5V

 

 

 

±1

A

IOZH

Off State HIGH-Level Output

VCC = Max., VOUT = 2.7V

 

 

 

10

A

 

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOZL

Off State LOW-Level

VCC = Max., VOUT = 0.5V

 

 

 

–10

A

 

 

Output Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

OS

Output Short Circuit Current[6]

V

= Max., V

= 0.0V

 

–60

–120

–225

mA

 

 

CC

OUT

 

 

 

 

 

 

IOFF

Power-Off Disable

VCC = 0V, VOUT = 4.5V

 

 

 

±1

A

Capacitance[5]

Parameter

Description

Typ.[4]

Max.

Unit

CIN

Input Capacitance

5

10

pF

COUT

Output Capacitance

9

12

pF

Notes:

 

 

 

 

4.Typical values are at VCC=5.0V, TA=+25˚C ambient.

5.This parameter is specified but not tested.

6.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

3

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