Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT480T
SCCS025 - May 1993 - Revised March 2000
Dual 8-Bit Parity Generator/Checker
Features
•Function, pinout and drive compatible with FCT and F logic
•FCT-A speed at 7.5 ns max. (Com’l) FCT-B speed at 5.6 ns max. (Com’l)
•Reduced VOH (typically = 3.3V) versions of equivalent FCT functions
•Edge-rate control circuitry for significantly improved noise characteristics
•Power-off disable feature
•Matched rise and fall times
•ESD > 2000V
•Fully compatible with TTL input and output logic levels
• Sink Current |
64 mA (Com’l), |
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32 mA (Mil) |
Source Current |
32 mA (Com’l), |
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12 mA (Mil) |
•Two 8-bit parity generator/checkers
•Open drain Active LOW parity error output
•Expandable for larger word widths
Functional Description
The FCT480T is a high-speed dual 8-bit parity generator/checker. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity error output. The FCT480T can be used in ODD parity systems. The parity error output is open-drain, designed for easy expansion of the word width by a wired-OR connection of several FCT480T type devices. Since additional logic is not needed, the parity generation or checking times remain the same as for an individual FCT480T device.
The outputs are designed with a power-off disable feature to allow for live insertion of boards.
Logic Block Diagram
A1
B1
C1
D1
E1
F1
G1
H1
PAR1
CHK/GEN
A2
B2
C2
D2
E2
F2
G2
H2
PAR2
Pin Configurations
LCC
Top View
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1 |
H G |
NC F |
E |
D |
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PAR |
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1 1 |
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1 |
1 |
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1 |
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1110 9 |
8 |
7 |
6 |
5 |
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CHK/GEN |
C1 |
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12 |
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4 |
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ODD1 |
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B1 |
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13 |
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3 |
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GND |
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A1 |
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14 |
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2 |
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NC |
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NC |
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15 |
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1 |
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ODD2 |
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VCC |
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16 |
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28 |
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ERROR |
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17 |
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27 |
A2 |
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PAR2 |
18 |
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26 |
B2 |
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19 20 21 22 23 24 25 |
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2 |
2 |
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2 2 |
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H |
G |
F |
NC E D |
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FCT480T–2
ODD1
ERR
ODD2
FCT480T–1
DIP/SOIC/QSOP
Top View
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A1 |
1 |
24 |
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VCC |
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2 |
23 |
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B1 |
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A2 |
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3 |
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C1 |
22 |
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B2 |
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4 |
21 |
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D1 |
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C2 |
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5 |
20 |
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E1 |
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D2 |
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6 |
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F1 |
19 |
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E2 |
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G1 |
7 |
18 |
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F2 |
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H1 |
8 |
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17 |
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G2 |
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PAR1 |
9 |
16 |
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H2 |
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CHK/GEN |
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10 |
15 |
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PAR2 |
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ODD |
1 |
11 |
14 |
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ERROR |
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GND |
12 |
13 |
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2 |
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ODD |
FCT480T–3
Copyright © 2000, Texas Instruments Incorporated
CY54/74FCT480T
Function Table
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Inputs |
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Outputs |
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A1 to H1 |
A2 to H2 |
CHK/GEN |
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PAR1 |
PAR2 |
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ODD1 |
ODD2 |
ERROR |
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Number of A1 to H1 Inputs |
Number of A2 to H2 Inputs |
H |
H |
H |
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L |
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L |
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H |
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HIGH is EVEN |
HIGH is EVEN |
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Number of Inputs HIGH A2 |
H |
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to H2 is ODD |
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Number of A1 to H1 Inputs |
Number of A2 to H2 Inputs |
H |
H |
H |
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L |
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HIGH is ODD |
HIGH is EVEN |
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Number of A2 to H2 Inputs |
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HIGH is ODD |
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Maximum Ratings[1, 2]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. |
–65°C to +150°C |
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Ambient Temperature with |
–65°C to +135°C |
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Power Applied ............................................. |
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Supply Voltage to Ground Potential ............... |
–0.5V to +7.0V |
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DC Input Voltage............................................ |
–0.5V to +7.0V |
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DC Output Voltage ......................................... |
–0.5V to +7.0V |
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DC Output Current (Maximum Sink Current/Pin)....... |
120 mA |
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Power Dissipation .......................................................... |
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0.5W |
Static Discharge Voltage............................................ |
>2001V |
(per MIL-STD-883, Method 3015) |
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Operating Range
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Ambient |
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Range |
Range |
Temperature |
VCC |
Commercial |
All |
–40°C to +85°C |
5V ± 5% |
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Military[3] |
All |
–55°C to +125°C |
5V ± 10% |
Notes:
1.Unless otherwise noted, these limits are over the operating free-air temperature range.
2.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
3.TA is the “instant on” case temperature.
2
CY54/74FCT480T
Electrical Characteristics Over the Operating Range
Parameter |
Description |
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Test Conditions |
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Min. |
Typ.[4] |
Max. |
Unit |
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VOH |
Output HIGH Voltage |
VCC = Min., IOH = –32 mA |
Com’l |
2.0 |
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V |
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VCC = Min., IOH = –15 mA |
Com’l |
2.4 |
3.3 |
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V |
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VCC = Min., IOH = –12 mA |
Mil |
2.4 |
3.3 |
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V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 64 mA |
Com’l |
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0.3 |
0.55 |
V |
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VCC = Min., IOL = 32 mA |
Mil |
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0.3 |
0.55 |
V |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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VH |
Hysteresis[5] |
All inputs |
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0.2 |
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V |
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VIK |
Input Clamp Diode Voltage |
VCC = Min., IIN = –18 mA |
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–0.7 |
–1.2 |
V |
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II |
Input HIGH Current |
VCC = Max., VIN = VCC |
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5 |
A |
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IIH |
Input HIGH Current |
VCC = Max., VIN = 2.7V |
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±1 |
A |
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IIL |
Input LOW Current |
VCC = Max., VIN = 0.5V |
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±1 |
A |
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IOZH |
Off State HIGH-Level Output |
VCC = Max., VOUT = 2.7V |
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10 |
A |
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Current |
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IOZL |
Off State LOW-Level |
VCC = Max., VOUT = 0.5V |
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–10 |
A |
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Output Current |
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I |
OS |
Output Short Circuit Current[6] |
V |
= Max., V |
= 0.0V |
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–60 |
–120 |
–225 |
mA |
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CC |
OUT |
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IOFF |
Power-Off Disable |
VCC = 0V, VOUT = 4.5V |
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±1 |
A |
Capacitance[5]
Parameter |
Description |
Typ.[4] |
Max. |
Unit |
CIN |
Input Capacitance |
5 |
10 |
pF |
COUT |
Output Capacitance |
9 |
12 |
pF |
Notes: |
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4.Typical values are at VCC=5.0V, TA=+25˚C ambient.
5.This parameter is specified but not tested.
6.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.
3