Texas Instruments CD74HCT377M, CD74HCT377E, CD74HC377M96, CD74HC377M, CD74HC377E Datasheet

Data sheet acquired from Harris Semiconductor SCHS184

CD74HC377,

CD74HCT377

September 1997

High Speed CMOS Logic Octal D-Type Flip-Flop with Data Enable

		Features		VCC = 5V
		•	Buffered Common Clock	• HCT Types
				- 4.5V to 5.5V Operation
	[ /Title	•	Buffered Inputs
				- Direct LSTTL Input Logic Compatibility,
	(CD74
		•	Typical Propagation Delay = 17ns at CL = 15pF,	VIL= 0.8V (Max), VIH = 2V (Min)
	HC377		VCC = 5V, TA = 25oC	- CMOS Input Compatibility, I ≤ 1μA at V , V
	,				l	OL	OH
		•	Fanout (Over Temperature Range)	Description
	CD74		- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
	HCT37
			- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads	The Harris CD74HC377 and CD74HCT377 are octal D-type
	7)	• Wide Operating Temperature Range . . . -55oC to 125oC		flip-flops with a buffered clock (CP) common to all eight flip-
	/Sub-			flops. All the flip-flops are loaded		simultaneously on the
		•	Balanced Propagation Delay and Transition Times	positive edge of the clock (CP) when the Data Enable (E) is
	ject
				Low.
	(High	•	Significant Power Reduction Compared to LSTTL
	Speed		Logic ICs	Ordering Information
	CMOS	• HC Types
							PKG.
	Logic		- 2V to 6V Operation		TEMP. RANGE (oC)
				PART NUMBER		PACKAGE	NO.
	Octal		- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
				CD74HC377E	-55 to 125	20 Ld PDIP	E20.3
	D-
	Type
		Pinout
	Flip-
			CD74HC377, CD74HCT377

(PDIP, SOIC)

TOP VIEW

E	1	20	VCC
Q0	2	19	Q7

D0

3

18 D7

D1

4

17 D6

Q1

5

16 Q6

Q2

6

15 Q5

D2

7

14 D5

D3

8

13 D4

Q3

9

12 Q4

GND

10

11 CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1675.1

Copyright © Harris Corporation 1997

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CD74HC377, CD74HCT377

Functional Diagram

3									2
D0												Q0
4									5
D1												Q1
7									6
D2												Q2
8									9
D3												Q3
13									12
D4												Q4
14									15
D5												Q5
17									16
D6												Q6
18									19
D7												Q7
11							1
CP									GND = 10
									VCC = 20
	E

TRUTH TABLE

		INPUTS				OUPUTS
OPERATING MODE	CP		E		Dn	Qn
Load “1”	−		l		h	H
Load “0”	−		l		l	L
Hold (Do Nothing)	−		h		X	No Change
	X	H			X	No Change
NOTES:
H = High Voltage Level Steady State.
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
L = Low Voltage Level Steady State.
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
X = Don’t Care.
− = Low to High Clock Transition.

Logic Diagram

D0 D1 D2 D3 D4 D5 D6 D7

E

D Q	D Q	D Q	D Q	D Q	D Q	D Q	D Q
CP	CP	CP	CP	CP	CP	CP	CP
CP
Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7

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CD74HC377, CD74HCT377

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 3)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 100
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS		VCC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or VIL	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-4	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-5.2	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or VIL	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			4	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			5.2	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND
Quiescent Device	ICC	VCC or	0	6	-	-	8	-	80	-	160	μA
Current		GND

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