Texas Instruments CD74HCT368M96, CD74HCT368M, CD74HCT368E, CD74HCT367M96, CD74HCT367M Datasheet
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Data sheet acquired from Harris Semiconductor SCHS181
November 1997
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
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Description |
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Buffered Inputs |
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The Harris CD74HC367, CD74HCT367, CD74HC368, and |
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[ /Title |
• High Current Bus Driver Outputs |
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CD74HCT368 silicon gate CMOS three-state buffers are gen- |
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eral purpose high-speed non-inverting and inverting buffers. |
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(CD74 |
• Two Independent Three-State Enable Controls |
They have high drive current outputs which enable high speed |
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HC367 |
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Typical Propagation Delay t |
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PHL |
= 8ns at V |
= 5V, |
operation even when driving large bus capacitances. These cir- |
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PLH |
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cuits possess the low power dissipation of CMOS circuitry, yet |
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= 15pF, T = 25oC |
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have speeds comparable to low power Schottky TTL circuits. |
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CD74 |
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• Fanout (Over Temperature Range) |
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Both circuits are capable of driving up to 15 low power Schottky |
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HCT36 |
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- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads |
inputs. |
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7, |
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- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads |
The CD74HC367 and CD74HCT367 are non-inverting buffers, |
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CD74 |
• Wide Operating Temperature Range . . . -55oC to 125oC |
whereas the CD74HC368 and CD74HCT368 are inverting buff- |
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ers. These devices have two output enables, one enable (OE1) |
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HC368 |
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Balanced Propagation Delay and Transition Times |
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controls 4 gates and the other (OE2) controls the remaining 2 |
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• Significant Power Reduction Compared to LSTTL |
gates. |
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CD74 |
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The CD74HCT367 and CD74HCT368 logic families are speed, |
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HCT36 |
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Logic ICs |
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• HC Types |
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function and pin compatible with the standard 74LS logic family. |
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8) |
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Ordering Information |
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/Sub- |
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- 2V to 6V Operation |
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ject |
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- High Noise Immunity: NIL = 30%, NIH = 30% of VCC |
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TEMP. RANGE |
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at VCC = 5V |
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PART NUMBER |
(oC) |
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PACKAGE |
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PKG. NO. |
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(High |
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• HCT Types |
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CD74HC367E |
-55 to 125 |
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16 Ld PDIP |
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E16.3 |
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Speed |
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- 4.5V to 5.5V Operation |
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CD74HCT367E |
-55 to 125 |
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16 Ld PDIP |
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E16.3 |
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- Direct LSTTL Input Logic Compatibility, |
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CD74HCT368E |
-55 to 125 |
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16 Ld PDIP |
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E16.3 |
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VIL= 0.8V (Max), VIH = 2V (Min) |
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CD74HC367M |
-55 to 125 |
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16 Ld SOIC |
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M16.15 |
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- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH |
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CD74HCT367M |
-55 to 125 |
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16 Ld SOIC |
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M16.15 |
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CD74HC368M |
-55 to 125 |
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16 Ld SOIC |
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M16.15 |
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CD74HCT368M |
-55 to 125 |
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16 Ld SOIC |
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M16.15 |
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NOTES: |
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1. When ordering, use the entire part number. Add the suffix 96 to |
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obtain the variant in the tape and reel. |
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2. Wafer or die for this part number is available which meets all |
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electrical specifications. Please contact your local sales office or |
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Harris customer service for ordering information. |
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Pinouts |
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CD74HC367, CD74HCT367 |
(PDIP, SOIC) |
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CD74HC368, CD74HCT368 (PDIP, SOIC) |
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TOP VIEW |
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TOP VIEW |
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OE1 |
1 |
16 VCC |
OE1 |
1 |
16 VCC |
1A |
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15 OE2 |
1A |
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15 OE2 |
1Y |
3 |
14 |
6A |
1Y |
3 |
14 |
6A |
2A |
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13 |
6Y |
2A |
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13 |
6Y |
2Y |
5 |
12 |
5A |
2Y |
5 |
12 |
5A |
3A |
6 |
11 |
5Y |
3A |
6 |
11 |
5Y |
3Y |
7 |
10 |
4A |
3Y |
7 |
10 |
4A |
GND |
8 |
9 |
4Y |
GND |
8 |
9 |
4Y |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1538.1 |
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Copyright © Harris Corporation 1997
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CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Functional Diagrams
CD74HC367, CD74HCT367 |
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16 |
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OE1 |
VCC |
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2 |
15 |
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1A |
OE2 |
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3 |
14 |
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1Y |
6A |
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4 |
13 |
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2A |
6Y |
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5 |
12 |
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2Y |
5A |
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6 |
11 |
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3A |
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5Y |
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7 |
10 |
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3Y |
4A |
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8 |
9 |
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GND |
4Y |
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CD74HC368, CD74HCT368 |
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1 |
16 |
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OE1 |
VCC |
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2 |
15 |
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1A |
OE2 |
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3 |
14 |
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1Y |
6A |
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4 |
13 |
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2A |
6Y |
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5 |
12 |
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2Y |
5A |
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6 |
11 |
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3A |
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5Y |
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7 |
10 |
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4A |
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3Y |
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8 |
9 |
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GND |
4Y |
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TRUTH TABLE
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OUTPUTS |
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INPUTS |
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(Y) |
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A |
HC/HCT367 |
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HC/HCT368 |
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OE |
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L |
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L |
L |
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H |
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L |
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H |
H |
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L |
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H |
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X |
(Z) |
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(Z) |
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NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
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CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Logic Diagram
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VCC |
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16 |
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ONE OF SIX IDENTICAL CIRCUITS |
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2 |
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1A |
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(NOTE) |
3 |
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1Y |
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GND |
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8 |
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1 |
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OE1 |
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4 |
5 |
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15 |
2A |
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2Y |
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OE2 |
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6 |
7 |
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3A |
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3Y |
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10 |
9 |
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4A |
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4Y |
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12
5A
11
5Y
14
6A
13
6Y
NOTE: Inverter not included in HC/HCT367.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
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