Texas Instruments CD74HCT4094M96, CD74HCT4094E, CD74HC4094PWR, CD74HC4094PW, CD74HC4094NSR Datasheet

Data sheet acquired from Harris Semiconductor SCHS211

November 1997

CD74HC4094,

CD74HCT4094

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

		Features
		•	Buffered Inputs
	[ /Title	•	Separate Serial Outputs Synchronous to Both
	(CD74H		Positive and Negative Clock Edges For Cascading
	C4094,	•	Fanout (Over Temperature Range)
	CD74H		- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
	CT4094		- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
	)	•	Wide Operating Temperature Range . . . -55oC to 125oC
	/Sub-	•	Balanced Propagation Delay and Transition Times
	ject
		•	Significant Power Reduction Compared to LSTTL
	(High
			Logic ICs
	Speed
		• HC Types
	CMOS
			- 2V to 6V Operation
	Logic 8-

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Pinout

CD74HC4094, CD74HCT4094

(PDIP, SOIC)

TOP VIEW

STROBE

1

16 VCC

DATA

2

15 OE

CP	3	14	Q4
Q0	4	13	Q5

Q1	5	12	Q6
Q2	6	11	Q7

Q3

7

10 QS2

GND

8

9

QS1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1779.1

Copyright © Harris Corporation 1997

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CD74HC4094, CD74HCT4094

Description

The Harris CD74HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means

for cascading these devices when the clock rise time is slow.

Ordering Information

	TEMP. RANGE (oC)		PKG.
PART NUMBER		PACKAGE	NO.
CD74HC4094E	-55 to 125	16 Ld PDIP	E16.3
CD74HCT4094E	-55 to 125	16 Ld PDIP	E16.3
CD74HC4094M	-55 to 125	16 Ld SOIC	M16.15
CD74HCT4094M	-55 to 125	16 Ld SOIC	M16.15
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Functional Diagram

2						9
DATA				8-STAGE				QS1
3				SHIFT		10
				REGISTER
CP								QS2
1				8-BIT
STROBE				STORAGE
				REGISTER
						4		Q0
						5
								Q1
						6
								Q2
						7
				THREE-				Q3
15
						14
OE				STATE				Q4
				OUTPUT		13
								Q5
						12
								Q6	GND = 8
						11
								Q7	VCC = 16

TRUTH TABLE

	INPUTS				PARALLEL OUTPUTS		SERIAL OUTPUTS
CP	OE		STR	D	Q0	Qn	QS1 (NOTE 4)	QS2
−	L		X	X	Z	Z	Q’6	NC
↓	L		X	X	Z	Z	NC	Q7
−	H		L	X	NC	NC	Q’6	NC
−	H		H	L	L	Qn -1	Q’6	NC

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CD74HC4094, CD74HCT4094

TRUTH TABLE

	INPUTS				PARALLEL OUTPUTS		SERIAL OUTPUTS
CP	OE		STR	D	Q0	Qn	QS1 (NOTE 4)	QS2
−	H		H	H	H	Qn -1	Q’6	NC
↓	H		H	H	NC	NC	NC	Q7

NOTES:

3.H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state, − = Transition from Low to High Level, ↓ = Transition from High to Low.

4.At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.

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