Texas Instruments CY74FCT16841CTPVCT, CY74FCT16841CTPVC, CY74FCT16841ATPVC, CY74FCT162841CTPVC, CY74FCT162841CTPAC Datasheet

Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.

CY74FCT16841T

CY74FCT162841T

SCCS067 - July 1994 - Revised March 2000

20-Bit Latches

Features

•FCT-C speed at 5.5 ns (FCT16841T Com’l)

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for significantly improved noise characteristics

•Typical output skew < 250 ps

•ESD > 2000V

•TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages

•Industrial temperature range of−40˚C to +85˚C

•VCC = 5V ± 10%

CY74FCT16841T Features:
• 64 mA sink current, 32 mA source current
• Typical V	(ground bounce) <1.0V at V	CC	= 5V,
OLP

TA = 25˚C

CY74FCT162841T Features:

•Balanced 24 mA output drivers

•Reduced system switching noise

• Typical V	(ground bounce) <0.6V at V	CC	= 5V,
OLP
TA= 25˚C

Functional Description

The CY74FCT16841T and CY74FCT162841T are 20-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 10-bit latches, or as a single 10-bit latch, or as a single 20-bit latch by connecting the Output Enable (OE) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. The output buffers are designed with a power-off disable feature to allow live insertion of boards.

The CY74FCT16841T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162841T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162841T is ideal for driving transmission lines.

Logic Block Diagrams	Pin Configuration
	SSOP/TSSOP
	Top View

1OE

1LE

1D1

D

1Q1

C

TO 9 OTHER CHANNELS

2OE

2LE

2D1

D

C

FCT16841-1

2Q1

TO 9 OTHER CHANNELS

FCT16841-2

1OE				1	56	1LE
1Q1						1D1
				2	55
1Q2						1D2
				3	54
GND				4	53	GND
						1D3
1Q3				5	52
1Q4						1D4
				6	51
VCC						VCC
				7	50
1Q5						1D5
				8	49
1Q6						1D6
				9	48
1Q7						1D7
				10	47
GND						GND
				11	46
1Q8						1D8
				12	45
1Q9						1D9
				13	44
1Q10						1D10
				14	43
2Q1						2D1
				15	42
2Q2				16	41	2D2
2Q3						2D3
				17	40
GND				18	39	GND
						2D4
2Q4				19	38
						2D5
		Q		20	37
2		5				2D6
2Q6				21	36
VCC				22	35	VCC
2Q7				23	34	2D7
2Q8						2D8
				24	33
GND				25	32	GND
2Q9						2D9
				26	31
2Q10				27	30	2D10
2	OE			28	29	2LE

FCT16841-3

Copyright © 2000, Texas Instruments Incorporated

CY74FCT16841T

CY74FCT162841T

Pin Description

	Name		Description
	D		Data Inputs
	LE		Latch Enable Input (Active HIGH)
			Output Enable Input (Active LOW)
	OE
	O		Three-State Outputs

Function Table[1]

	Inputs				Outputs
D	LE				Q
			OE
H	H		L		H
L	H		L		L
X	L		L		Q[2]
X	X		H		Z

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ......................................	−55°C to +125°C
Ambient Temperature with	−55°C to +125°C
Power Applied ..................................................
DC Input Voltage .................................................	−0.5V to +7.0V
DC Output Voltage ..............................................	−0.5V to +7.0V
DC Output Current	−60 to +120 mA
(Maximum Sink Current/Pin) ...........................

Power Dissipation ..........................................................	1.0W
Static Discharge Voltage............................................	>2001V
(per MIL-STD-883, Method 3015)

Operating Range

	Ambient
Range	Temperature	VCC
Industrial	−40°C to +85°C	5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter		Description			Test Conditions			Min.	Typ.[5]	Max.	Unit
VIH		Input HIGH Voltage	Logic HIGH Level					2.0			V
VIL		Input LOW Voltage	Logic LOW Level							0.8	V
VH		Input Hysteresis[6]							100		mV
VIK		Input Clamp Diode Voltage	VCC=Min., IIN=−18 mA						−0.7	−1.2	V
IIH		Input HIGH Current	VCC=Max., VI=VCC							±1	µA
IIL		Input LOW Current	VCC=Max., VI=GND							±1	µA
IOZH		High Impedance Output	VCC=Max., VOUT=2.7V							±1	µA
		Current (Three-State Output pins)
IOZL		High Impedance Output	VCC=Max., VOUT=0.5V							±1	µA
		Current (Three-State Output pins)
I	OS	Short Circuit Current[7]	V	CC	=Max., V		=GND	−80	−140	−200	mA
					OUT
I	O	Output Drive Current[7]	V	CC	=Max., V		=2.5V	−50		−180	mA
					OUT
I	OFF	Power-Off Disable	V	CC	=0V, V	≤4.5V[8]				±1	µA
					OUT

Notes:

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.

2.Output level before LE HIGH-to-LOW Transition.

3.Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.

4.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5.Typical values are at VCC= 5.0V, TA= +25˚C ambient.

6.This parameter is specified but not tested.

7.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

8.Tested at +25˚C.

2