Texas Instruments CD74HCT573M96, CD74HCT573M, CD74HCT573E, CD74HCT373M96, CD74HCT373M Datasheet

[ /Title (CD74 HC373

,

CD74

HCT37

3,

CD54

HC573

,

CD74

HC573

,

CD74

HCT57

3) /Sub-

Data sheet acquired from Harris Semiconductor SCHS182

November 1997

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573

High Speed CMOS Logic Octal Transparent Latch, Three-State Output

Features

•Common Latch Enable Control

•Common Three-State Output Enable Control

•Buffered Inputs

•Three-State Outputs

•Bus Line Driving Capacity

•Typical Propagation Delay = 12ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output for HC373)

•Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The Harris CD74HC373, CD74HCT373, CD54HC573, CD74HC573, and CD74HCT573 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. The CD74HCT373 and CD74HCT573 are functionally as well as pin compatible with the standard 74LS373 and 74LS573.

The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (OE) controls the threestate outputs. When the output enable (OE) is high the outputs are in the high impedance state. The latch operation is independent to the state of the output enable. The 373 and 573 are identical in function and differ only in their pinout arrangements.

Ordering Information

	TEMP. RANGE		PKG.
PART NUMBER	(oC)	PACKAGE	NO.
CD54HC573F	-55 to 125	20 Ld CERDIP	F20.3
CD74HC373E	-55 to 125	20 Ld PDIP	F20.3
CD74HCT373E	-55 to 125	20 Ld PDIP	E20.3
CD74HC573E	-55 to 125	20 Ld PDIP	E20.3
CD74HCT573E	-55 to 125	20 Ld PDIP	E20.3
CD74HC373M	-55 to 125	20 Ld SOIC	M20.3
CD74HCT373M	-55 to 125	20 Ld SOIC	M20.3
CD74HC573M	-55 to 125	20 Ld SOIC	M20.3
CD74HCT573M	-55 to 125	20 Ld SOIC	M20.3
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Wafer or die for this part number are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1679.1
Copyright © Harris Corporation 1997	1

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573

Pinout

CD74HC373, CD74HCT373

(PDIP, SOIC)

TOP VIEW

OE	1	20	VCC
Q0	2	19	Q7

D0

3

18

D7

D1

4

17

D6

Q1

5

16

Q6

Q2

6

15

Q5

D2

7

14

D5

D3

8

13

D4

Q3

9

12

Q4

GND 10

11 LE

CD54HC573, CD74HC573, CD74HCT573

(PDIP, SOIC, CERDIP)

TOP VIEW

OE	1	20	VCC
D0	2	19	Q0

D1

3

18

Q1

D2

4

17

Q2

D3

5

16

Q3

D4	6	15	Q4
D5	7	14	Q5

D6

8

13

Q6

D7

9

12

Q7

GND 10

11 LE

Functional Block Diagrams
	CD74HC373, CD74HCT373, CD74HC573, CD74HCT573
D0	D1	D2	D3	D4	D5	D6	D7
D	D	D	D	D	D	D		D
G O	G O	G O	G O	G O	G O	G O		G O
LE
OE
	O0	O1	O2	O3	O4	O5	O6	O7
			CD74HCT573
D0	D1	D2	D3	D4	D5	D6	D7
D O	D O	D O	D O	D O	D O	D O		D O
G	G	G	G	G	G	G		G
LE
OE
	O0	O1	O2	O3	O4	O5	O6	O7

TRUTH TABLE

	OUTPUT ENABLE		LATCH ENABLE			DATA	OUTPUT
	L				H	H	H
	L				H	L	L
	L				L	l	L
	L				L	h	H
	H				X	X	Z

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.

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CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±35mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information

Thermal Resistance (Typical, Note 3). . . .	θJA (oC/W) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .	125	N/A
CERDIP Package . . . . . . . . . . . . . . . .	85	24
SOIC Package . . . . . . . . . . . . . . . . . . .	120	N/A
Maximum Junction Temperature (Plastic Package) .		. . . . . . . 150oC
Maximum Storage Temperature Range .	. . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .		. . . . . . . 300oC

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
Voltage
			-7.8	6	5.48	-	-	5.34	-	5.2	-	V
TTL Loads
Low Level Output	VOL	VIH or	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage		VIL
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			6	4.5	-	-	0.26	-	0.33	-	0.4	V
Voltage
			7.8	6	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND
Quiescent Device	ICC	VCC or	0	6	-	-	8	-	80	-	160	μA
Current		GND

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