[ /Title (CD54 HC405 1, CD74 HC405 1, CD74 HCT40 51, CD74 HC405 2,
Data sheet acquired from Harris Semiconductor SCHS122A
November 1997 - Revised April 1999
CD54HC4051, CD74HC4051, CD74HCT4051, CD74HC4052, CD74HCT4052, CD74HC4053, CD74HCT4053
High Speed CMOS Logic Analog Multiplexers/Demultiplexers
Features
• Wide Analog Input Voltage Range . . . . . . . . . .±5V Max
•Low “On” Resistance
-70Ω Typical (VCC - VEE = 4.5V)
-40Ω Typical (VCC - VEE = 9V)
•Low Crosstalk between Switches
•Fast Switching and Propagation Speeds
•“Break-Before-Make” Switching
• Wide Operating Temperature Range . . -55oC to 125oC
• CD54HC/CD74HC Types |
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Operation Control Voltage . . . . |
. . . . . . . . . . 2V to 6V |
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- |
Switch Voltage . . . . . . . |
. . . . . . . . |
. . . . . . . . 0V to 10V |
- |
High Noise Immunity . . . |
NIL = 30%, NIH = 30% of VCC, |
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VCC = 5V |
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• CD54HCT/CD74HCT Types |
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Operation Control Voltage . . . . . |
. . . . . . 4.5V to 5.5V |
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Switch Voltage . . . . . . . |
. . . . . . . . |
. . . . . . . . 0V to 10V |
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Direct LSTTL Input |
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Logic Compatibility . . . |
VIL = 0.8V Max, VIH = 2V Min |
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CMOS Input Compatibility . . . . . |
II ≤ 1μA at VOL, VOH |
Description
These devices are digitally controlled analog switches which utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range (i.e. VCC to VEE). They are bidirectional switches thus allowing any analog input to be used as an output and visa-versa. The switches have low “on” resistance and low “off” leakages. In addition, all three devices have an enable control which, when high, disables all switches to their “off” state.
Ordering Information
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TEMP. |
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PKG. |
PART NUMBER |
RANGE (oC) |
PACKAGE |
NO. |
CD54HC4051F |
-55 to 125 |
16 Ld CERDIP |
F16.3 |
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CD74HC4051E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HC4052E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HC4053E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HCT4051E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HCT4052E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HCT4053E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
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CD74HC4051M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HC4052M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HC4053M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HCT4051M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HCT4052M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HCT4053M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
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CD74HCT4053PW |
-55 to 125 |
16 Ld TSSOP |
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CD74HCT4052SM |
-55 to 125 |
16 Ld SSOP |
M16.15A |
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NOTES: |
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1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. For the TSSOP package only, add the suffix R to obtain the variant in the tape and reel.
2.Wafer or die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1676.1 |
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Copyright © Harris Corporation 1997 |
1 |
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CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53
Pinouts
CD54HC4051
CD74HC4051, CD74HCT4051
(CERDIP, PDIP, SOIC)
TOP VIEW
CHANNEL |
A4 |
1 |
IN/OUT |
A6 |
2 |
|
COM OUT/IN |
A |
3 |
CHANNEL |
A7 |
4 |
IN/OUT |
A5 |
5 |
|
E |
6 |
VEE |
7 |
GND |
8 |
16 VCC |
15 |
A2 |
14 |
A1 |
CHANNEL |
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13 |
A0 |
IN/OUT |
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12 |
A3 |
11 |
S0 |
10 S1 |
ADDRESS |
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SELECT |
9 |
S2 |
CD74HC4052, CD74HCT4052
(PDIP, SOIC)
TOP VIEW
CHANNEL |
B0 |
1 |
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IN/OUT |
B2 |
2 |
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COM OUT/IN BN |
3 |
CHANNEL |
B3 |
4 |
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IN/OUT |
B1 |
5 |
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E |
6 |
VEE |
7 |
GND |
8 |
16 VCC |
15 |
A2 |
CHANNEL |
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14 |
A1 |
IN/OUT |
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13 |
AN |
COM OUT/IN |
12 |
A0 |
CHANNEL |
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11 |
A3 |
IN/OUT |
10 |
S0 |
9 |
S1 |
CD74HC4053, CD74HCT4053
(PDIP, SOIC, TSSOP)
TOP VIEW
B1 |
1 |
CHANNEL |
B0 |
2 |
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IN/OUT |
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C1 |
3 |
COM OUT/IN CN |
4 |
IN/OUT C0 |
5 |
E |
6 |
VEE |
7 |
GND |
8 |
16 VCC |
15 |
BN |
COM OUT/IN |
14 |
AN |
COM OUT/IN |
13 |
A1 |
CHANNEL |
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12 |
A0 |
IN/OUT |
11 |
S0 |
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10 |
S1 |
9 |
S2 |
2
CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53
Functional Diagram of HC/HCT4051
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CHANNEL IN/OUT |
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VCC |
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
16 |
4 |
2 |
5 |
1 |
12 |
15 |
14 |
13 |
TG |
TG
S0 11
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TG |
S1 |
10 |
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TG |
BINARY |
A |
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3 COMMON |
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LOGIC |
TO |
OUT/IN |
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1 OF 8 |
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LEVEL |
TG |
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DECODER |
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CONVERSION |
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WITH |
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S2 |
9 |
ENABLE |
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TG |
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TG |
E |
6 |
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TG |
8 |
7 |
GND VEE
TRUTH TABLE
CD54/74HC/HCT4051
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INPUT STATES |
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“ON” |
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ENABLE |
S2 |
S1 |
S0 |
CHANNELS |
L |
L |
L |
L |
A0 |
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L |
L |
L |
H |
A1 |
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L |
L |
H |
L |
A2 |
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L |
L |
H |
H |
A3 |
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L |
H |
L |
L |
A4 |
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L |
H |
L |
H |
A5 |
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L |
H |
H |
L |
A6 |
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L |
H |
H |
H |
A7 |
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H |
X |
X |
X |
None |
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X = Don’t care
3
CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53
Functional Diagram of HC/HCT4052
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A CHANNELS IN/OUT |
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VCC |
A3 |
A2 |
A1 |
A0 |
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11 |
15 |
14 |
12 |
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16 |
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BINARY |
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S1 |
9 |
LOGIC |
TO |
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1 OF 4 |
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LEVEL |
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CONVERSION |
DECODER |
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WITH |
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ENABLE |
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S0 |
10 |
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E |
6 |
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8 |
7 |
GND VEE
TRUTH TABLE
CD74HC4052, CD74HCT4052
|
INPUT STATES |
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“ON” |
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ENABLE |
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S1 |
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S0 |
CHANNELS |
L |
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L |
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L |
A0, B0 |
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L |
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L |
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H |
A1, B1 |
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L |
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H |
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L |
A2. B2 |
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L |
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H |
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H |
A3, B3 |
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H |
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X |
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X |
None |
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X = Don’t care
1 |
5 |
2 |
4 |
B0 |
B1 |
B2 |
B3 |
B CHANNELS IN/OUT
TG
TG
TG |
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TG |
13 |
COMMON A |
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OUT/IN |
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TG |
3 |
COMMON B |
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OUT/IN |
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TG |
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TG
TG
4
CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53
Functional Diagram of HC/HCT4053
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VCC |
BINARY TO |
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IN/OUT |
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1 OF 2 |
C1 |
C0 |
B1 |
B0 |
A1 |
A0 |
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LOGIC LEVEL |
16 |
DECODERS |
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CONVERSION |
WITH ENABLE |
3 |
5 |
1 |
2 |
13 |
12 |
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TG |
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14 |
A COMMON |
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OUT/IN |
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S0 |
11 |
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TG |
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TG |
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S1 |
10 |
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15 |
B COMMON |
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OUT/IN |
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TG |
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S2 |
9 |
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TG |
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C COMMON |
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4 |
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OUT/IN |
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TG |
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E |
6 |
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8 |
7 |
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GND |
VEE |
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TRUTH TABLE
CD74HC4053, CD74HCT4053
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INPUT STATES |
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“ON” |
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ENABLE |
S0 |
S1 |
S2 |
CHANNELS |
L |
L |
L |
L |
C0, B0, A0 |
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L |
H |
L |
L |
C0, B0, A1 |
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L |
L |
H |
L |
C0, B1, A0 |
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L |
H |
H |
L |
C0, B1, A1 |
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L |
L |
L |
H |
C1, B0, A0 |
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L |
H |
L |
H |
C1, B0, A1 |
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L |
L |
H |
H |
C1, B1, A0 |
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L |
H |
H |
H |
C1, B1, A1 |
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H |
X |
X |
X |
None |
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X = Don’t care
5
CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53
Absolute Maximum Ratings (Note 3) |
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Thermal Information |
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DC Supply Voltage, V |
CC |
- V . . . . . . . . . . . . . . . . . |
-0.5V to 10.5V |
Thermal Resistance (Typical, Note 4) |
θ |
JA |
(oC/W) θ |
JC |
(oC/W) |
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EE |
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DC Supply Voltage, VCC |
. . . . . . . . . . . . . . . . . . . . . . . . . |
. . . -0.5V to +7V |
PDIP Package . . . . . . . . . . . . . . . . . . . |
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90 |
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N/A |
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DC Supply Voltage, VEE . |
. . . . . . . . . . . . . . . . . . . . . . . . . |
. . +0.5V to -7V |
SOIC Package . . . . . . . . . . . . . . . . . . . |
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160 |
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N/A |
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DC Input Diode Current, IIK |
±20mA |
CERDIP Package . . . . . . . . . . . . . . . . |
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130 |
|
55 |
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For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . |
TSSOP Package . . . . . . . . . . . . . . . . . |
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149 |
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35 |
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DC Switch Diode Current, IOK |
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Maximum Junction Temperature . . . . . . . . |
. . |
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. . . . . . . . . |
. . |
. 150oC |
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For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . |
. . . . . .±20mA |
Maximum Storage Temperature Range . . . |
. |
. . |
. . . .-65oC to 150oC |
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DC Switch Current, (Note 2) |
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Maximum Lead Temperature (Soldering 10s) . . |
. . . . . . . . |
. . |
. 300oC |
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For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . |
. . . . . .±25mA |
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DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . |
. . . . . .±50mA |
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DC VEE Current, IEE |
. . . |
. . . . . . . . . . . . . . . . . . . . . . . |
. . . . . -20mA |
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Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges
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PARAMETER |
MIN |
MAX |
UNITS |
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Supply Voltage Range (For TA = Full Package Temperature Range), VCC (Note 5) |
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CD54/74HC Types |
2 |
6 |
V |
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CD54/74HCT Types |
4.5 |
5.5 |
V |
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Supply Voltage Range (For TA = Full Package Temperature Range), VCC - VEE |
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CD54/74HC Types, CD54/74HCT Types (See Figure 1) |
2 |
10 |
V |
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Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 5) |
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CD54/74HC Types, CD54/74HCT Types (See Figure 2) |
0 |
-6 |
V |
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DC Input Control Voltage, VI |
GND |
VCC |
V |
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Analog Switch I/O Voltage, VIS |
VEE |
VCC |
V |
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Operating Temperature, T |
-55 |
125 |
oC |
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A |
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Input Rise and Fall Times, tr, tf |
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2V |
0 |
1000 |
ns |
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4.5V |
0 |
500 |
ns |
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6V |
0 |
400 |
ns |
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CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3.All voltages referenced to GND unless otherwise specified.
4.θJA is measured with the component mounted on an evaluation PC board in free air.
5.In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal-
culated from rON values shown in Electrical Specifications table). No VCC current will flow through RL if the switch current flows into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053.
Recommended Operating Area as a Function of Supply Voltages
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8 |
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(V) |
6 |
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GND |
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HC |
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HCT |
4 |
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- |
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CC |
2 |
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V |
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0 |
2 |
4 |
6 |
8 |
10 |
12 |
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0 |
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VCC - VEE (V) |
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8 |
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(V) |
6 |
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GND |
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HCT |
HC |
4 |
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- |
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CC |
2 |
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V |
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0 |
-2 |
-4 |
-6 |
-8 |
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0 |
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VEE - GND (V) |
FIGURE 1. |
FIGURE 2. |
6