Texas Instruments CD74HCT563M, CD74HCT563E, CD74HCT533E, CD74HC533E, CD74HC563M Datasheet

CD74HC533, CD74HCT533,

[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed

Data sheet acquired from Harris Semiconductor
SCHS187

January 1998

Features

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capacity

• Typical Propagation Delay = 13ns at V
C

= 15pF, TA = 25oC (Data to Output)

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

CD74HC563, CD74HCT563

High Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

Description

The Harris CD74HC533, CD74HCT533, CD74HC563, and
CD74HCT563 are high speed Octal Transparent Latches
manufactured with silicon gate CMOS technology. They pos­sess the low power consumption of standard CMOS inte­grated circuits, as well as the ability to drive 15 LSTTL
devices.

The outputs are transparent to the inputs when the latch

C to 125oC

CC

OH

enable (
data is latched. The output enable (
state outputs. When the output enable (
outputs are in the high impedance state. The latch operation
is independent to the state of the output enable.

The CD74HC533 and CD74HCT533 are identical in function
to the CD74HC563 and CD74HCT563 but have different
pinouts. The CD74HC533 and CD74HCT533 are similar to
the CD74HC373 and CD74HCT373; the latter are non­inverting types.

Ordering Information

NOTES:

LE) is high. When the latch enable (LE) goes lo w the

OE) controls the three-

OE) is high the

TEMP. RANGE

PART NUMBER

CD74HC533E -55 to 125 20 Ld PDIP F20.3
CD74HCT533E -55 to 125 20 Ld PDIP E20.3
CD74HC563E -55 to 125 20 Ld PDIP E20.3
CD74HCT563E -55 to 125 20 Ld PDIP E20.3
CD74HCT563M -55 to 125 20 Ld SOIC M20.3

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number are available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1599.1

Pinouts

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

CD74HC533, CD74HCT533

(PDIP, SOIC)

TOP VIEW

1

OE

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

Functional Block Diagram

LE

D

0

D
G

D

O

CD74HC563, CD74HCT563

(PDIP, SOIC)

TOP VIEW

V

20

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

LE 11

OE

D0
D1
D2
D3
D4
D5
D6
D7

GND

1
2
3
4
5
6
7
8
9

10

CD74HC/HCT533

1

D

2

O

D
G

D

3

O

D
G

D

4

O

D
G

D

5

O

D
G

D

6

O

D
G

D
G

V

20

CC

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13
12

Q7
LE

D

7

O

O

D
G

OE

O

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

TRUTH TABLE

OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT

LHHL
LHLH
LLlH
LLhL

HXXZ

NOTE: H = High Voltage Level, L = Low VoltageLevel, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.

2

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

25

C -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSV

3