Texas Instruments CD74HCT4075E, CD74HC4075PWR, CD74HC4075M96, CD74HC4075M, CD74HC4075E Datasheet
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Data sheet acquired from Harris Semiconductor SCHS210
August 1997
CD74HC4075,
CD74HCT4075
High Speed CMOS Logic
Triple 3-Input OR Gate
[ /Title (CD74H C4075, CD74H CT4075) /Subject (High Speed CMOS Logic Triple 3- Input
Features
•Buffered Inputs
•Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
Description
The Harris CD74HC4075, CD74HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.
Ordering Information
|
TEMP. RANGE (oC) |
|
PKG. |
PART NUMBER |
PACKAGE |
NO. |
|
CD74HC4075E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
|
|
|
|
CD74HC4075E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
|
|
|
|
CD74HC4075M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
|
|
|
|
CD74HC4075M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
|
|
|
|
CD54HC4075H |
-55 to 125 |
Die |
|
|
|
|
|
CD54HCT4075H |
-55 to 125 |
Die |
|
|
|
|
|
CD54HC4075W |
-55 to 125 |
Wafer |
|
|
|
|
|
CD54HCT4075W |
-55 to 125 |
Wafer |
|
|
|
|
|
NOTE: When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD74HC4075, CD74HCT4075
(PDIP, SOIC)
TOP VIEW
2A |
1 |
|
14 |
VCC |
2B |
|
|
|
3C |
2 |
|
13 |
||
1A |
|
|
|
3B |
3 |
|
12 |
||
1B |
|
|
|
3A |
4 |
|
11 |
||
1C |
|
|
|
3Y |
5 |
|
10 |
||
1C |
|
|
|
2Y |
6 |
|
9 |
||
GND |
|
|
|
2C |
7 |
|
8 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1778.1 |
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||
Copyright © Harris Corporation 1997 |
1 |
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CD74HC4075, CD74HCT4075
Functional Diagram
3 |
|
|
1A |
|
|
4 |
6 |
|
1B |
1Y |
|
5 |
|
|
1C |
|
|
1 |
|
|
2A |
|
|
2 |
9 |
|
2Y |
||
2B |
||
8 |
|
|
2C |
|
|
11 |
|
|
3A |
|
|
12 |
10 |
|
3Y |
||
3B |
||
13 |
GND = 7 |
|
3C |
VCC = 14 |
TRUTH TABLE
|
INPUTS |
|
OUTPUT |
|
|
|
|
nA |
nB |
nC |
nY |
|
|
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|
L |
L |
L |
L |
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|
H |
X |
X |
H |
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|
X |
H |
X |
H |
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X |
X |
H |
H |
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NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Diagram
nA
nB |
nY |
nC
2
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