Texas Instruments CD74HCT670M96, CD74HCT670M, CD74HCT670E, CD74HC670M96, CD74HC670M Datasheet

Data sheet acquired from Harris Semiconductor SCHS195

January 1998

CD74HC670,

CD74HCT670

High-Speed CMOS Logic

4x4 Register File

Features

at VCC = 5V

•

Simultaneous and Independent Read and Write

• HCT Types

- 4.5V to 5.5V Operation

[ /Title

Operations

•

Expandable to 512 Words of n-Bits

- Direct LSTTL Input Logic Compatibility,

(CD74H

VIL= 0.8V (Max), VIH = 2V (Min)

C670,

•

Three-State Outputs

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

CD74H

•

Organized as 4 Words x 4 Bits Wide

Description

CT670)

•

Buffered Inputs

/Subject

•

Typical Read Time = 16ns for CD74HC670 V

= 5V, C

The Harris CD74HC670 and CD74HCT670 are 16-bit register

files organized as 4 words x 4 bits each. Read and write

(High-

CC

L

= 15pF, TA = 25oC

address and enable inputs allow simultaneous writing into one

Speed

• Fanout (Over Temperature Range)

location while reading another. Four data inputs are provided

CMOS

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

to store the 4-bit word. The write address inputs (WA0 and

Logic

WA1) determine the location of the stored word in the register.

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

4x4 Reg-

When write enable (WE) is low the word is entered into the

• Wide Operating Temperature Range . . . -55oC to 125oC

ister

address location and it remains transparent to the data. The

•

Balanced Propagation Delay and Transition Times

outputs will reflect the true form of the input data. When (WE)

is high data and address inputs are inhibited. Data acquisition

• Significant Power Reduction Compared to LSTTL

from the four registers is made possible by the read address

Logic ICs

inputs (RA1 and RA0). The addressed word appears at the

• HC Types

output when the read enable

(RE)

is low. The output is in the

high impedance state when the (RE) is high. Outputs can be

- 2V to 6V Operation

tied together to increase the word capacity to 512 x 4 bits.

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

Ordering Information

Pinout

CD74HC670, CD74HCT670

(PDIP, SOIC)

TOP VIEW

D1

1

16 VCC

D2

2

15

D0

D3

3

14 WA0

RA1

4

13 WA1

RA0

5

12 WE

Q3

6

11 RE

Q2

7

10

Q0

GND

8

9

Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1660.1

Copyright © Harris Corporation 1998

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CD74HC670, CD74HCT670

Functional Diagram

		D0		15						10	Q0
				1						9	Q1
		D1
				2						7
		D2
											Q2
				3
		D3								6
				12							Q3
	WE
				11
		RE
RA1				4		5	14	13
RA0
WA0
WA1

WRITE MODE SELECT TABLE

			INPUTS			INTERNAL
OPERATING						LATCHES
MODE					DN	(NOTE 3)
		WE
Write Data		L			L	L
		L			H	H
Data Latched		H			X	No Change
NOTE:

3.The Write Address (WA0 and WA1) to the “internal latches” must be stable while WE is LOW for conventional operation.

READ MODE SELECT TABLE

			INPUTS
				INTERNAL
OPERATING				LATCHES	OUTPUT
MODE				(NOTE 4)	QN
		RE
Read		L		L	L
		L		H	H
Disabled		H		X	(Z)
NOTE:

4.The selection of the “internal latches” by Read Address (RA0 and RA1) are not constrained by WE or RE operation.

H = High Voltage Level L = Low Voltage Level X= Don’t Care

Z = High Impedance “Off” State

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CD74HC670, CD74HCT670

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±35mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 5)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 160
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

5. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS		VCC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or VIL	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-7.8	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or VIL	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			6	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			7.8	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND

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