Texas Instruments CD74HCT75E, CD74HC75E, CD74HC75PWR, CD74HC75M96, CD74HC75M Datasheet

Data sheet acquired from Harris Semiconductor SCHS135

March 1998

CD74HC75,

CD74HCT75

Dual 2-Bit Bistable

Transparent Latch

Features

at VCC = 5V

•

True and Complementary Outputs

• HCT Types

- 4.5V to 5.5V Operation

[ /Title

•

Buffered Inputs and Outputs

- Direct LSTTL Input Logic Compatibility,

(CD74

•

Fanout (Over Temperature Range)

VIL= 0.8V (Max), VIH = 2V (Min)

HC75,

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH

CD74

-

Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Description

HCT75

•

Wide Operating Temperature Range . . . -55oC to 125oC

)

•

Balanced Propagation Delay and Transition Times

The Harris CD74HC75 and CD74HCT75 are dual 2-bit

/Sub-

bistable transparent latches. Each one of the 2-bit latches is

•

Significant Power Reduction Compared to LSTTL

ject

controlled by separate Enable inputs

(1E

and

2E)

which are

Logic ICs

active LOW. When the Enable input is HIGH data enters the

(Dual

• HC Types

latch and appears at the Q output. When the Enable input

2-Bit

(1E and 2E) is LOW the output is not affected.

-

2V to 6V Operation

Bistabl

Ordering Information

-

High Noise Immunity: NIL = 30%, NIH = 30% of VCC

e

Pinout

CD74HC75, CD74HCT75

(PDIP, SOIC)

TOP VIEW

1Q0

1

16

1Q0

1D0

2

15

1Q1

1D1

3

14

1Q1

2E	4	13	1E
VCC	5	12	GND

2D0

6

11

2Q0

2D1

7

10

2Q0

2Q1

8

9

2Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1666.1

Copyright © Harris Corporation 1998

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CD74HC75, CD74HCT75

Functional Diagram

	2 (6)						16 (10)		Q0
							1 (11)
	D0
					1 OF 2				Q0
	3 (7)						14 (8)
					LATCHES
									Q1
	D1						15 (9)
									Q1
					13 (4)
		E

TRUTH TABLE

	INPUTS					OUTPUTS
	D				Q
			E						Q
	L		H		L				H
	H		H		H				L
	X		L		Q0
								Q0
NOTE:
H	= High Level
L	= Low Level
X	= Don’t Care

Q0 = The level of Q before the transition of E.

	LATCH 0		16 (10)
2 (6)
D0	D	Q	Q0
	LE	LE	1 (11)
13 (4)			Q0
E			LE	LE

			14 (8)	P		P
				Q		N
			Q1	N
3 (7)	LE	LE		LE	Q	LE
			15 (9)
D1	D	Q	Q1
	LATCH 1

5 VCC

12 GND

FIGURE 1. LOGIC DIAGRAM

FIGURE 2. LATCH DETAIL

2

CD74HC75, CD74HCT75

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±25mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 3)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.	90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.	115
Maximum Junction Temperature (Hermetic Package or Die) . .		. 175oC
Maximum Junction Temperature (Plastic Package) .	. . . . . .	. 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . .	. 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
				4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
				6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-4	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-5.2	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage		VIL
				4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
				6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			4	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			5.2	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	µA
Current		GND

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