Texas Instruments CY74FCT163500CPACT, CY74FCT163500CPAC, CY74FCT163500APVCT, CY74FCT163500APVC, CY74FCT163500CPVCT Datasheet

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Texas Instruments CY74FCT163500CPACT, CY74FCT163500CPAC, CY74FCT163500APVCT, CY74FCT163500APVC, CY74FCT163500CPVCT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

CY74FCT163500

SCCS066 - June 1997 - Revised March 2000

18-Bit Registered Transceiver

Features

• Low power, pin-compatible replacement for LCX and LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 4.6 ns

• Latch-up performance exceeds JEDEC standard no. 17

• ESD > 2000V per MIL-STD-883D, Method 3015

• Typical output skew < 250ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

• Typical V (ground bounce) performance exceeds Mil olp

Std 883D

• VCC = 2.7V to 3.6V

Functional Description

The CY74FCT163500 is an 18-bit universal bus transceiver that can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA.

The CY74FCT163500 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce.The inputs and outputs are capable of being driven by 5.0V busses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power off disable feature enabling them to be used in applications requiring live insertion.

Logic Block Diagram

 

 

Pin Configuration

 

 

 

 

SSOP/TSSOP

 

 

 

 

 

Top View

 

 

 

 

OEAB

1

56

GND

 

 

 

LEAB

2

55

CLKAB

 

 

 

A1

3

54

B1

OEAB

 

 

GND

4

53

GND

CLKBA

 

 

A2

5

52

B2

 

 

A3

6

51

B3

 

 

 

LEBA

 

 

VCC

7

50

VCC

OEBA

 

 

A4

8

49

B4

 

 

A5

9

48

B5

 

 

 

CLKAB

 

 

A6

10

47

B6

LEAB

 

 

GND

11

46

GND

 

 

A7

12

45

B7

 

 

 

 

C

C

A8

13

44

B8

 

A9

14

43

B9

 

 

 

 

 

 

B1

 

 

 

A1

D

D

A10

15

42

B

 

 

 

10

 

 

 

A11

16

41

B11

 

 

 

A12

17

40

B12

 

C

C

GND

18

39

GND

 

A13

19

38

B13

 

 

 

 

D

D

A14

20

37

B14

 

 

 

A15

21

36

B15

 

 

 

VCC

22

35

VCC

 

 

 

A16

23

34

B16

 

TO 17 OTHER CHANNELS

A17

24

33

B17

 

GND

25

32

GND

 

 

 

 

 

 

A18

26

31

B18

 

 

 

OEBA

27

30

CLKBA

 

 

 

LEBA

28

29

GND

 

 

 

 

 

Copyright © 2000, Texas Instruments Incorporated

CY74FCT163500

Pin Summary

 

Name

Description

 

OEAB

A-to-B Output Enable Input

 

 

 

 

 

 

 

 

 

B-to-A Output Enable Input (Active LOW)

 

OEBA

 

 

 

 

LEAB

A-to-B Latch Enable Input

 

 

 

 

LEBA

B-to-A Latch Enable Input

 

 

 

 

 

 

 

 

A-to-B Clock Input (Active LOW)

 

CLKAB

 

 

 

 

 

 

 

 

B-to-A Clock Input (Active LOW)

 

CLKBA

AA-to-B Data Inputs or B-to-A Three-State Outputs

BB-to-A Data Inputs or A-to-B Three-State Outputs

Maximum Ratings[5, 6]

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................

−55°C to +125°C

Ambient Temperature with

−55°C to +125°C

Power Applied .................................................

Supply Voltage Range .....................................

0.5V to +4.6V

DC Input Voltage .................................................

−0.5V to +7.0V

DC Output Voltage ..............................................

−0.5V to +7.0V

DC Output Current

−60 to +120 mA

(Maximum Sink Current/Pin) ...........................

Power Dissipation ..........................................................

1.0W

Function Table[1, 2]

 

Inputs

 

 

Outputs

 

 

 

 

 

 

 

 

OEAB

LEAB

 

 

 

 

A

B

CLKAB

 

 

 

 

 

 

 

 

L

X

 

X

 

X

Z

 

 

 

 

 

 

 

 

H

H

 

X

 

L

L

 

 

 

 

 

 

 

 

H

H

 

X

 

H

H

 

 

 

 

 

 

 

 

H

L

 

 

 

 

L

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

L

 

 

 

 

H

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

L

 

H

 

X

B[3]

H

L

 

L

 

X

B[4]

Notes:

Static Discharge Voltage............................................

>2001V

(per MIL-STD-883, Method 3015)

 

Operating Range

 

 

 

 

 

 

 

 

Ambient

 

Range

 

Temperature

VCC

Industrial

 

−40°C to +85°C

2.7V to 3.6V

 

 

 

 

1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition.

2.A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.

3.Output level before the indicated steady-state input conditions were established.

4.Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.

5.Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.

6.Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

2

CY74FCT163500

Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V

 

Parameter

Description

 

 

 

Test Conditions

Min.

Typ.[7]

Max.

Unit

VIH

Input HIGH Voltage

 

All Inputs

 

 

 

2.0

 

5.5

 

V

VIL

Input LOW Voltage

 

 

 

 

 

 

 

 

 

0.8

 

V

VH

Input Hysteresis[8]

 

 

 

 

 

 

 

 

100

 

 

mV

VIK

Input Clamp Diode Voltage

 

VCC=Min., IIN=−18 mA

 

−0.7

−1.2

V

IIH

Input HIGH Current

 

VCC=Max., VI=5.5V

 

 

±1

 

µA

IIL

Input LOW Current

 

VCC=Max., VI=GND.

 

 

±1

 

µA

IOZH

High Impedance Output Current

 

VCC=Max., VOUT=5.5V

 

 

±1

 

µA

 

 

(Three-State Output pins)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOZL

High Impedance Output Current

 

VCC=Max., VOUT=GND

 

 

±1

 

µA

 

 

(Three-State Output pins)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IODL

Output LOW Current[9]

 

VCC=3.3V, VIN=VIH

45

 

180

 

mA

 

 

 

 

or VIL, VOUT=1.5V

 

 

 

 

 

I

ODH

Output HIGH Current[9]

 

V

CC

=3.3V, V

IN

=V

IH

–45

 

–180

mA

 

 

 

 

or VIL, VOUT=1.5V

 

 

 

 

 

VOH

Output HIGH Voltage

 

VCC=Min., IOH= –0.1 mA

VCC–0.2

 

 

 

V

 

 

 

 

VCC=3.0V, IOH= –8 mA

2.4

3.0

 

 

V

 

 

 

 

VCC=3.0V, IOH= –24 mA

2.0

3.0

 

 

V

VOL

Output LOW Voltage

 

VCC=Min., IOL= 0.1mA

 

 

0.2

 

V

 

 

 

 

VCC=Min., IOL= 24 mA

 

0.3

0.5

 

 

I

OS

Short Circuit Current[9]

 

V

=Max., V

 

=GND

–60

–135

–240

mA

 

 

 

 

CC

OUT

 

 

 

 

 

 

IOFF

Power-Off Disable

 

VCC=0V, VOUT≤4.5V

 

 

±100

 

µA

Capacitance[8] (T = +25˚C, f = 1.0 MHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Description

 

 

 

Test Conditions

 

Typ.[7]

Max.

 

Unit

CIN

Input Capacitance

VIN = 0V

 

 

 

 

 

4.5

6.0

 

pF

COUT

Output Capacitance

VOUT = 0V

 

 

 

 

5.5

8.0

 

pF

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

 

7.Typical values are at VCC=3.3V, TA = +25˚C ambient.

8.This parameter is specified but not tested.

9.Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last.

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