Texas Instruments CY74FCT16652ETPVCT, CY74FCT16652ETPVC, CY74FCT16652ETPACT, CY74FCT16652ETPAC, CY74FCT16652CTPVCT Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

CY74FCT16652T

CY74FCT162652T

SCCS061 - July 1994 - Revised March 2000

Features

•FCT-E speed at 3.8 ns

•Power-off disable outputs permits live insertion

•Edge-rate control circuitry for significantly improved noise characteristics

•Typical output skew < 250 ps

•ESD > 2000V

•TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages

•Industrial temperature range of−40˚C to +85˚C

•VCC = 5V ± 10%

CY74FCT16652T Features:
• 64 mA sink current, 32 mA source current
• Typical V	(ground bounce) <1.0V at V	CC	= 5V,
OLP

TA = 25˚C

CY74FCT162652T Features:

•Balanced 24 mA output drivers

•Reduced system switching noise

• Typical V	(ground bounce) <0.6V at V	CC	= 5V,
OLP
TA= 25˚C

16-Bit Registered Transceivers

Functional Description

These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The output buffers are designed with a power-off disable feature that allows live insertion of boards.

The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines.

Logic Block Diagrams
1OEAB			2OEAB
1OEBA			2OEBA
1CLKBA			2CLKBA
1SBA			2SBA
1CLKAB			2CLKAB
1SAB	B REG		2SAB	B REG
	D			D
	C			C
1A1			2A1
	A REG		A REG
	D		D
	C	1B1	C		2B1
	TO 7 OTHER CHANNELS	FCT16652-1		TO 7 OTHER CHANNELS	FCT16652-2

Copyright © 2000, Texas Instruments Incorporated

CY74FCT16652T

CY74FCT162652T

			Pin Configuration
					SSOP/TSSOP
						Top View
			1OEAB
					1	56			1	OEBA
									1CLKBA
			1CLKAB		2	55
			1SAB						1SBA
					3	54
			GND		4	53				GND
									1B1
			1A1		5	52
			1A2						1B2
					6	51
			VCC						VCC
					7	50
			1A3						1B3
					8	49
			1A4						1B4
					9	48
			1A5						1B5
					10	47
			GND		11	46			GND
			1A6		12	45			1B6
									1B7
			1A7		13	44
			1A8						1B8
					14	43
									2B1
			2A1		15	42
			2A2						2B2
					16	41
									2B3
			2A3		17	40
									GND
			GND		18	39
									2B4
			2A4		19	38
			2A5						2B5
					20	37
			2A6						2B6
					21	36
			VCC						VCC
					22	35
									2B7
			2A7		23	34
			2A8						2B8
					24	33
						FCT16652–1			GND
			GND		25	32
			2SAB		26	31			2SBA
			2CLKAB		27	30			2CLKBA
			2OEAB		28	29			2		OEBA
									FCT16652-3
Pin Description
	Name										Description
A			Data Register A Inputs
			Data Register B Outputs
B			Data Register B Inputs
			Data Register A Outputs
CLKAB, CLKBA			Clock Pulse Inputs
SAB, SBA			Output Data Source Select Inputs
OEAB,			Output Enable Inputs
	OEBA

2

CY74FCT16652T

CY74FCT162652T

Function Table[1]

Inputs

Data I/O[2]

OEAB

CLKAB

CLKBA

SAB

SBA

A

B

Operation or Function

OEBA

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

X

X

Store A and B Data

X

H

H or L

X

X

Input

Unspecified[2]

Store A, Hold B

H

H

X[3]

X

Input

Output

Store A in Both Registers

L

X

H or L

X

X

Unspecified[2]

Input

Hold A, Store B

L

L

X

X[3]

Input

Store B in both Registers

L

L

X

X

X

L

Output

Input

Real Time B Data to A Bus

L

L

X

H or L

X

H

Stored B Data to A Bus

H

H

X

X

L

X

Input

Output

Real Time A Data to B Bus

H

H

H or L

X

H

X

Stored A Data to B Bus

H

L

H or L

H or L

H

H

Output

Output

Stored A Data to B Bus and

Stored B Data to A Bus

Notes:

1.H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

=LOW-to-HIGH Transition

2.The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

3.Select control=L; clocks can occur simultaneously.

Select control=H; clocks must be staggered to load both registers.

3