[ /Title (CD74 HC393
,
CD74
HCT39
3) /Subject (High Speed CMOS
Data sheet acquired from Harris Semiconductor SCHS186
September 1997
CD74HC393,
CD74HCT393
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
Features
•Fully Static Operation
•Buffered Inputs
•Common Reset
•Negative-Edge Clocking
•Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF, TA = 25oC
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
Description
The Harris CD74HC393 and CD74HCT393 are 4-stage ripple-carry binary counters. Al counter stages are masterslave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.
Ordering Information
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TEMP. RANGE (oC) |
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PKG. |
PART NUMBER |
PACKAGE |
NO. |
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CD74HC393E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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CD74HCT393E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
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1CP |
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1 |
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14 |
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VCC |
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1MR |
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2 |
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13 |
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2CP |
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1Q0 |
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2MR |
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3 |
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12 |
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1Q1 |
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2Q0 |
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4 |
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11 |
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1Q2 |
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2Q1 |
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5 |
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10 |
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1Q3 |
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2Q2 |
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6 |
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9 |
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GND |
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2Q3 |
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7 |
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8 |
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CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1653.1 |
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Copyright © Harris Corporation 1997 |
1 |
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CD74HC393, CD74HCT393
Functional Diagram
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1 |
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3 |
1Q0 |
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4 |
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1CP |
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BINARY |
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1Q1 |
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2 |
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5 |
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1MR |
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COUNTER |
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1Q2 |
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6 |
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1Q3 |
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11 |
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13 |
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2Q0 |
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10 |
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2CP |
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BINARY |
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2Q1 |
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12 |
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9 |
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2MR |
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COUNTER |
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2Q2 |
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8 |
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2Q3 |
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GND = 7 |
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VCC = 14 |
TRUTH TABLE
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OUTPUTS |
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CP COUNT |
Q0 |
Q1 |
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Q2 |
Q3 |
0 |
L |
L |
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L |
L |
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1 |
H |
L |
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L |
L |
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2 |
L |
H |
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L |
L |
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3 |
H |
H |
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L |
L |
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4 |
L |
L |
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H |
L |
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5 |
H |
L |
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H |
L |
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6 |
L |
H |
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H |
L |
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7 |
H |
H |
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H |
L |
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8 |
L |
L |
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L |
H |
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9 |
H |
L |
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L |
H |
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10 |
L |
H |
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L |
H |
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11 |
H |
H |
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L |
H |
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12 |
L |
L |
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H |
H |
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13 |
H |
L |
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H |
H |
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14 |
L |
H |
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H |
H |
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15 |
H |
H |
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H |
H |
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CP COUNT |
MR |
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OUTPUT |
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− |
L |
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No Change |
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↓ |
L |
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Count |
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X |
H |
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L L L L |
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NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, − = Transition from Low to High Level, ↓ = Transition from High to Low.
2
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CD74HC393, CD74HCT393 |
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Logic Diagram |
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Φ |
Q |
Φ |
Q |
Φ |
Q |
Φ |
Q |
1(13) |
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CP |
Φ |
Q |
Φ |
Q |
Φ |
Q |
Φ |
Q |
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R |
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R |
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R |
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R |
2(12) |
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MR |
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3(11) |
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4(10) |
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5(9) |
6(8) |
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Q0 |
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Q1 |
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Q2 |
Q3 |
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3 |
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