Texas Instruments CD74HCT237E, CD74HCT137M96, CD74HCT137E, CD74HC237M96, CD74HC237M Datasheet

				CD74HC137, CD74HCT137,
	Data sheet acquired from Harris Semiconductor			CD74HC237, CD74HCT237
				High Speed CMOS Logic, 3-to-8 Line Decoder
	SCHS146
	March 1998				Demultiplexer with Address Latches
	Features
	•	Select One of Eight Data Outputs
[ /Title		-	Active Low for CD74HC137 and CD74HCT137
		-	Active High for CD74HC237 and CD74HCT237
(CD74
	•	l/O Port or Memory Selector
HC137
,	•	Two Enable Inputs to Simplify Cascading
CD74	•	Typical Propagation Delay of 13ns at VCC = 5V,
HCT13		15pF, TA = 25oC (CD74HC237)
7,	•	Fanout (Over Temperature Range)
CD74		- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
HC237		-	Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
,	•	Wide Operating Temperature Range . . . -55oC to 125oC
CD74	•	Balanced Propagation Delay and Transition Times
HCT23
	•	Significant Power Reduction Compared to LSTTL
7)
		Logic ICs
/Sub-
	• HC Types
ject
		-	2V to 6V Operation
(High
		-	High Noise Immunity: NIL = 30%, NIH = 30%, of VCC
Speed
			at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Pinout

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

(PDIP, SOIC)

TOP VIEW

A0	1	16	VCC
A1	2	15	Y0

A3	3	14	Y1
LE	4	13	Y2
OE1	5	12	Y3
OE0	6	11	Y4

Y7	7	10	Y5
GND	8	9	Y6

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1886.1

Copyright © Harris Corporation 1998

1

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

Description

The Harris CD74HC137, CD74HC237 and CD74HCT137, CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a “Low”; in the CD74HC237 and CD74HCT237 the selected output is a “High”.

Ordering Information

	TEMP. RANGE (oC)		PKG.
PART NUMBER		PACKAGE	NO.
CD74HC137E	-55 to 125	16 Ld PDIP	E16.3
CD74HCT137E	-55 to 125	16 Ld PDIP	E16.3
CD74HC237E	-55 to 125	16 Ld PDIP	E16.3
CD74HC237M	-55 to 125	16 Ld SOIC	M16.15
CD74HCT237E	-55 to 125	16 Ld PDIP	E16.3
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

2

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

Functional Diagram

HC/HCT HC/HCT

237

137

1

15

A0

Y0

Y

0

2

3-BIT

14

A1

LATCH

1 OF 8

Y1

Y1

3

DECODER

13

A2

Y2

Y2

12

4

Y3

3

LE

Y

11

Y4

4

Y

10

Y5

5

5

Y

9

1

Y6

6

OE

Y

6

7

OE0

Y7

Y

7

GND =

8

VCC = 16

CD74HC137, CD74HCT137 TRUTH TABLE

INPUTS

OUTPUTS

LE

OE0

1

A2

A1

A0

0

1

2

3

4

5

6

7

OE

Y

Y

Y

Y

Y

Y

Y

Y

X

X

H

X

X

X

H

H

H

H

H

H

H

H

X

L

X

X

X

X

H

H

H

H

H

H

H

H

L

H

L

L

L

L

L

H

H

H

H

H

H

H

L

H

L

L

L

H

H

L

H

H

H

H

H

H

L

H

L

L

H

L

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

H

H

L

H

H

H

H

L

H

L

H

L

L

H

H

H

H

L

H

H

H

L

H

L

H

L

H

H

H

H

H

H

L

H

H

L

H

L

H

H

L

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD74HC237, CD74HCT237 TRUTH TABLE

INPUTS

OUTPUTS

LE

OE0

1

A2

A1

A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

OE

X

X

H

X

X

X

L

L

L

L

L

L

L

L

X

L

X

X

X

X

L

L

L

L

L

L

L

L

L

H

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

L

H

L

H

L

L

L

L

L

L

L

H

L

L

H

L

L

L

H

L

L

L

L

L

L

H

L

L

H

H

L

L

L

H

L

L

L

L

L

H

L

H

L

L

L

L

L

L

H

L

L

L

L

H

L

H

L

H

L

L

L

L

L

H

L

L

L

H

L

H

H

L

L

L

L

L

L

L

H

L

L

H

L

H

H

H

L

L

L

L

L

L

L

H

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

3