Texas Instruments CD74HCT175M96, CD74HCT175M, CD74HCT175E, CD74HC175M96, CD74HC175M Datasheet

Data sheet acquired from Harris Semiconductor SCHS160

August 1997

CD74HC175,

CD74HCT175

High Speed CMOS Logic Quad D-Type Flip-Flop with Reset

Features

Description

• Common Clock and Asynchronous Reset on Four

The Harris CD74HC175 and CD74HCT175 are high speed

D-Type Flip-Flops

Quad D-type Flip-Flops with individual D-inputs and Q,

[ /Title

Q

•

Positive Edge Pulse Triggering

complementary outputs. The devices are fabricated using

(CD74

silicon gate CMOS technology. They have the low power

HC175

•

Complementary Outputs

consumption advantage of standard CMOS ICs and the

,

•

Buffered Inputs

ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q,

outputs on

CD74

•

Typical fMAX = 50MHz at VCC = 5V, CL = 15pF,

Q

HCT17

the positive going edge of the clock pulse. All four Flip-Flops

T = 25oC

are controlled by a common clock (CP) and a common reset

5)

A

•

Fanout (Over Temperature Range)

(MR). Resetting is accomplished by a low voltage level

/Sub-

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

independent of the clock. All four Q outputs are reset to a

ject

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

logic 0 and all four

Q

outputs to a logic 1.

(High

•

o

o

C

Ordering Information

Speed

Wide Operating Temperature Range . . . -55 C to 125

•

Balanced Propagation Delay and Transition Times

CMOS

TEMP. RANGE

PKG.

•

Significant Power Reduction Compared to LSTTL

Logic

PART NUMBER

(oC)

PACKAGE

NO.

Logic ICs

Quad

• HC Types

CD74HC175E

-55 to 125

16 Ld PDIP

E16.3

D-

- 2V to 6V Operation

CD74HCT175E

-55 to 125

16 Ld PDIP

E16.3

Type

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

CD74HC175M

-55 to 125

16 Ld SOIC

M16.15

Flip-

at VCC = 5V

CD74HCT175M

-55 to 125

16 Ld SOIC

M16.15

• HCT Types

- 4.5V to 5.5V Operation

CD74HCT175W

-55 to 125

Wafer

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

NOTES:

- CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

Pinout

CD74HC175, CD74HCT175

(PDIP, SOIC)

TOP VIEW

MR

1

16

VCC

Q0	2	15	Q3
Q0	3	14	Q3
D0	4	13	D3
D1	5	12	D2

Q1	6	11	Q2
Q1	7	10	Q2
GND	8	9	CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1474.1

Copyright © Harris Corporation 1997

1

CD74HC175, CD74HCT175

Functional Diagram

	4			2
	D0	D	Q
				Q0
	9
	CP	CP		3
	1		Q
				Q0
	MR	R
	5			7
	D1	D	Q
				Q1
		CP		6
			Q
		R		Q1
	12			10
	D2	D	Q
				Q2
		CP		11
			Q
		R		Q2
	13			15
	D3	D	Q
				Q3
		CP		14
			Q
		R		Q3

TRUTH TABLE

			INPUTS			OUTPUTS
RESET			CLOCK CP	DATA Dn	Qn				n
	(MR)							Q
L			X	X	L			H
H			↑	H	H			L
H			↑	L	L			H
H			L	X	Q0					0
								Q

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.

Logic Diagram

CL
	CL		ONE OF FOUR F/F

4 (5, 12, 13)	D
Dn

p

n

CL

R

CL

p

n

CL

p

n

CL

CL

p

n

CL CL CL

CP

1

3( 6, 11, 14)

Qn

2( 7, 10, 15) Qn

MR	TO OTHER THREE F/F	8	16
CP	9
	TO OTHER THREE F/F
		GND	VCC

2

CD74HC175, CD74HCT175

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 3)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 110
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO +85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-4	4.5	3.98	-	-	3.84	-	3.7	-	V
Voltage
			-5.2	6	5.48	-	-	5.34	-	5.2	-	V
TTL Loads
Low Level Output	VOL	VIH or	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage		VIL
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			4	4.5	-	-	0.26	-	0.33	-	0.4	V
Voltage
			5.2	6	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	µA
Current		GND
Quiescent Device	ICC	VCC or	0	6	-	-	8	-	80	-	160	µA
Current		GND

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