Texas Instruments CD74HCT174M96, CD74HCT174M, CD74HCT174E, CD74HC174M96, CD74HC174M Datasheet

...
CD74HC174,
/ j
[ /Title (CD74 HC174 , CD74 HCT17
4) Sub­ect
(High Speed CMOS Logic Hex D­Type Flip­Flop
Data sheet acquired from Harris Semiconductor SCHS159
August 1997
Features
• Buffered Positive Edge Triggered Clock
• Asynchronous Common Reset
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
= 30%, NIH = 30% of V
IL
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
1µA at VOL, V
l
o
C to 125oC
CC
OH
CD74HCT174
High Speed CMOS Logic
Hex D-Type Flip-Flop with Reset
Description
The Harris CD74HC174 and CD74HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low pow er and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The input, when low, sets all outputs to a low state.
Each output can drive ten low power Schottky TTL equivalent loads. The CD74HCT174 is functional as well as, pin compatible to the 74LS174.
Ordering Information
TEMP.RANGE
PART NUMBER
CD74HC174E -55 to 125 16 Ld PDIP E16.3 CD74HCT174E -55 to 125 16 Ld PDIP E16.3 CD74HC174M -55 to 125 16 Ld SOIC M16.15 CD74HCT174M -55 to 125 16 Ld SOIC M16.15
(oC) PACKAGE
MR
PKG.
NO.
Pinout
CD74HCT174W -55 to 125 Wafer
NOTES:
1. When ordering,use theentire part number.Add the suffix 96 to obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
CD74HC174, CD74HCT174
(PDIP, SOIC)
TOP VIEW
MR
Q D D Q D Q
GND
1 2
0
3
0
4
1
5
1
6
2
7
2
8
16 15 14 13 12 11 10
9
V Q D D Q D Q CP
CC
5 5 4
4 3
3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
1
File Number 1608.1
Functional Diagram
CD74HC174, CD74HCT174
CP
MR
D
0
D
1
D
2
D
3
D
4
D
5
CP D R
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
TRUTH TABLE
INPUTS OUTPUT
RESET (MR) CLOCK CP DATA D
n
Q
n
LXXL
Logic Diagram
3 (4, 6, 11, 13, 14) D
D
n
1
MR
9
CP
H HH H LL HLXQ
0
NOTE: H = High Voltage Level, L = Low Voltage Level,X = Irrelevant,= Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established
C
L
p n
C
C
L
R
L
p n
C
L
CP
C
L
p n
C
C
L
C
L
L
p n
C
L
TO OTHER FIVE F/F
TO OTHER FIVE F/F
ONE OF SIX F/F
C
L
2 (5, 7, 10, 12, 15)
Q
816
V
Q
CC
n
2
CD74HC174, CD74HCT174
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
25oC -40oC TO +85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
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