Texas Instruments CD74HCT173E, CD74HCT173M96, CD74HCT173M, CD74HC173M96, CD74HC173M Datasheet

Data sheet acquired from Harris Semiconductor SCHS158

February 1998

CD74HC173,

CD74HCT173

High Speed CMOS Logic

Quad D-Type Flip-Flop, Three-State

		Features
		•	Three-State Buffered Outputs
	[ /Title	•	Gated Input and Output Enables
		•	Fanout (Over Temperature Range)
	(CD74H
	C173,		- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
			- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
	CD74H
		• Wide Operating Temperature Range . . . -55oC to 125oC
	CT173)
		•	Balanced Propagation Delay and Transition Times
	/Subject
		•	Significant Power Reduction Compared to LSTTL
	(High
			Logic ICs
	Speed	• HC Types
	CMOS		- 2V to 6V Operation
	Logic		- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
	Quad D-		at VCC = 5V
	Type	• HCT Types
			- 4.5V to 5.5V Operation
			- Direct LSTTL Input Logic Compatibility,
			VIL= 0.8V (Max), VIH = 2V (Min)
			- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Pinout

CD74HC173, CD74HC173

(PDIP, SOIC)

TOP VIEW

OE

1

16

VCC

OE2	2	15	MR
Q0	3	14	D0

Q1	4	13	D1
Q2	5	12	D2

Q3

6

11

D3

CP

7

10

E2

GND

8

9

E1

Description

The Harris CD74HC173 and CD74HCT173 high speed three-state quad D-type flip-flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus lines in bus oriented systems.

The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic “1” level. The input ENABLES allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic “1” level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the MASTER RESET (MR) input to a logic “1” level. The data outputs change state on the positive going edge of the clock.

The CD74HCT173 logic family is functionally, as well as pin compatible with the standard 74LS logic family.

Ordering Information

	TEMP. RANGE		PKG.
PART NUMBER	(oC)	PACKAGE	NO.
CD74HC173E	-55 to 125	16 Ld PDIP	E16.3
CD74HCT173E	-55 to 125	16 Ld PDIP	E16.3
CD74HC173M	-55 to 125	16 Ld SOIC	M16.15
CD74HCT173M	-55 to 125	16 Ld SOIC	M16.15
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1641.1
Copyright © Harris Corporation 1998	1

CD74HC173, CD74HCT173

Functional Diagram

	E1
	E2					10	9
14									3
	D0									Q0
13
	D1								4	Q1
12
	D2								5	Q2
11
	D3								6	Q3
7
	CP
15						1	2
MR
OE1
OE2

TRUTH TABLE

	INPUTS
		DATA ENABLE						DATA	OUTPUT
MR	CP							D	Qn
			E1			E2
H	X		X			X		X	L
L	L		X			X		X	Q0
L	−		H			X		X	Q0
L	−		X			H		X	Q0
L	−		L			L		L	L
L	−		L			L		H	H

NOTE:

When either OE1 or OE2 (or both) is (are) high the output is disabled to the high-impedance state, however, sequential operation of the flip-flops is not affected.

H = High Voltage Level

L = Low Voltage Level

X = Irrelevant

− = Transition from Low to High Level

Q0 = Level Before the Indicated Steady-State Input Conditions Were Established

2

		CD74HC173, CD74HCT173
	Logic Diagram
	9
	E1
	10
	E2			VCC
		D	Q
	14			P
	D0			3
	7			Q0
	CP	CP	Q	N
			R
	15
	MR
	1
	OE1
	2
	OE2
	13			4
	D1			Q1
	12	3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT		5
	D2			Q2
		IN DASHED ENCLOSURE
	11			6
	D3			Q3
		3