[ /Title (CD74 HC126
,
CD74
HCT12
6) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState)
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CD74HC126, |
Data sheet acquired from Harris Semiconductor |
CD74HCT126 |
SCHS144 |
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High Speed CMOS Logic |
November 1997 |
Quad Buffer, Three-State |
Features
•Three-State Outputs
•Separate Output Enable Inputs
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
Description
The Harris CD74HC126 and CD74HCT126 contain four independent three-state buffers, each having its own output enable input, which when “low” puts the output in the highimpedance state.
Ordering Information
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TEMP. RANGE |
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PKG. |
PART NUMBER |
(oC) |
PACKAGE |
NO. |
CD74HC126E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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CD74HCT126E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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CD74HC126M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
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CD74HCT126M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
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NOTES: |
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1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
Pinout
CD74HC126, CD74HC126
(PDIP, SOIC)
TOP VIEW
1OE |
1 |
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14 |
VCC |
1A |
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4OE |
2 |
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13 |
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1Y |
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4A |
3 |
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12 |
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2OE |
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4Y |
4 |
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11 |
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2A |
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3OE |
5 |
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10 |
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2Y |
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3A |
6 |
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9 |
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GND |
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3Y |
7 |
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8 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1772.1 |
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Copyright © Harris Corporation 1997 |
1 |
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CD74HC126, CD74HCT126
Functional Diagram
1 |
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1OE |
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2 |
3 |
1Y |
1A |
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4 |
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2OE |
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5 |
6 |
2Y |
2A |
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10 |
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3OE |
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9 |
8 |
3Y |
3A |
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13 |
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4OE |
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12 |
11 |
4Y |
4A |
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GND = 7 |
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VCC = 14 |
TRUTH TABLE
INPUTS |
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OUTPUTS |
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nA |
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nOE |
nY |
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H |
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H |
H |
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L |
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H |
L |
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X |
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L |
Z |
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NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State
Logic Diagram
P
nA |
nY |
n
nOE
2
CD74HC126, CD74HCT126
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . |
-0.5V to 7V |
DC Input Diode Current, IIK |
±20mA |
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . |
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DC Output Diode Current, IOK |
±20mA |
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . |
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DC Drain Current, per Output, IO |
±35mA |
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . |
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DC Output Source or Sink Current per Output Pin, IO |
±25mA |
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . |
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DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . |
. . . .±70mA |
Thermal Information |
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Thermal Resistance (Typical, Note 3) |
θJA (oC/W) |
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 90 |
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 175 |
Maximum Junction Temperature . . . . . . . . . . . . . . . . |
. . . . . . . 150oC |
Maximum Storage Temperature Range . . . . . . . . . . |
-65oC to 150oC |
Maximum Lead Temperature (Soldering 10s) . . . . . . |
. . . . . . . 300oC |
(SOIC - Lead Tips Only) |
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Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
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TEST |
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25oC |
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-40oC TO 85oC |
-55oC TO 125oC |
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CONDITIONS |
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PARAMETER |
SYMBOL |
VI (V) |
IO (mA) |
VCC (V) |
MIN |
TYP |
MAX |
MIN |
MAX |
MIN |
MAX |
UNITS |
HC TYPES |
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High Level Input |
VIH |
- |
- |
2 |
1.5 |
- |
- |
1.5 |
- |
1.5 |
- |
V |
Voltage |
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4.5 |
3.15 |
- |
- |
3.15 |
- |
3.15 |
- |
V |
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6 |
4.2 |
- |
- |
4.2 |
- |
4.2 |
- |
V |
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Low Level Input |
VIL |
- |
- |
2 |
- |
- |
0.5 |
- |
0.5 |
- |
0.5 |
V |
Voltage |
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4.5 |
- |
- |
1.35 |
- |
1.35 |
- |
1.35 |
V |
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6 |
- |
- |
1.8 |
- |
1.8 |
- |
1.8 |
V |
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High Level Output |
VOH |
VIH or |
-0.02 |
2 |
1.9 |
- |
- |
1.9 |
- |
1.9 |
- |
V |
Voltage |
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VIL |
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-0.02 |
4.5 |
4.4 |
- |
- |
4.4 |
- |
4.4 |
- |
V |
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CMOS Loads |
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-0.02 |
6 |
5.9 |
- |
- |
5.9 |
- |
5.9 |
- |
V |
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High Level Output |
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-6 |
4.5 |
3.98 |
- |
- |
3.84 |
- |
3.7 |
- |
V |
Voltage |
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-7.8 |
6 |
5.48 |
- |
- |
5.34 |
- |
5.2 |
- |
V |
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TTL Loads |
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Low Level Output |
VOL |
VIH or |
0.02 |
2 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
Voltage |
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VIL |
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0.02 |
4.5 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
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CMOS Loads |
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0.02 |
6 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
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Low Level Output |
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6 |
4.5 |
- |
- |
0.26 |
- |
0.33 |
- |
0.4 |
V |
Voltage |
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7.8 |
6 |
- |
- |
0.26 |
- |
0.33 |
- |
0.4 |
V |
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TTL Loads |
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Input Leakage |
II |
VCC or |
- |
6 |
- |
- |
±0.1 |
- |
±1 |
- |
±1 |
μA |
Current |
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GND |
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3