Texas Instruments CD74HCT163E, CD74HCT161M96, CD74HCT161M, CD74HCT161E, CD74HCT163M96 Datasheet
...
[ /Title (CD74 HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed
Data sheet acquired from Harris Semiconductor SCHS154
February 1998
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
High Speed CMOS Logic
Presettable Counters
Features
•CD74HC161, CD74HCT161 4-Bit Binary Counter, Asynchronous Reset
•CD74HC163, CD74HCT163 4-Bit Binary Counter, Synchronous Reset
•Synchronous Counting and Loading
•Two Count Enable Inputs for n-Bit Cascading
•Look-Ahead Carry for High-Speed Counting
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH
Ordering Information
|
TEMP. RANGE (oC) |
|
PKG. |
PART NUMBER |
PACKAGE |
NO. |
|
CD74HC161E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
|
|
|
|
CD74HC161M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
|
|
|
|
CD74HC163E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
|
|
|
|
CD74HC163M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
|
|
|
|
CD74HCT161E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
|
|
|
|
CD74HCT161M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
|
|
|
|
CD74HCT163E |
-55 to 125 |
16 Ld PDIP |
E16.3 |
|
|
|
|
CD74HCT163M |
-55 to 125 |
16 Ld SOIC |
M16.15 |
|
|
|
|
NOTES: |
|
|
|
1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
Description
The Harris CD74HC161, CD74HCT161, CD74HC163 and CD74HCT163 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The CD74HC161 and CD74HCT161 are asynchronous reset decade and binary counters, respectively; the CD74HC163 and CD74HCT163 devices decade and binary counters, respectively and are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset input, MR. In the CD74HC163 and CD74HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the CD74HC161 and CD74HCT161 types).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.
Pinout
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
MR |
1 |
16 VCC |
CP |
2 |
15 TC |
P0 |
3 |
14 |
Q0 |
P1 |
4 |
13 |
Q1 |
P2 |
5 |
12 |
Q2 |
P3 |
6 |
11 |
Q3 |
PE |
7 |
10 TE |
GND |
8 |
9 |
SPE |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1550.1 |
|
|
||
Copyright © Harris Corporation 1998 |
1 |
|
|
|
|
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Functional Diagram
|
|
|
|
P0 |
P1 |
P2 |
P3 |
|
|||||
|
|
|
3 |
|
4 |
|
5 |
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
9 |
|
|
|
|
|
|
|
|
14 |
Q0 |
|
|
|
|
|
|
|
|
|
|
||||
SPE |
|
|
|
|
|||||||||
|
2 |
|
|
|
|
|
|
|
|
13 |
|||
|
CP |
|
|
|
|
|
|
|
Q1 |
||||
|
1 |
|
|
|
|
|
|
|
|
12 |
|||
|
|
|
|
|
|
|
|
|
|
Q2 |
|||
|
MR |
|
|
|
|
||||||||
|
|
7 |
|
|
|
|
|
|
|
|
11 |
||
|
PE |
|
|
|
|
|
|
|
Q3 |
||||
|
10 |
|
|
|
|
|
|
|
|
15 |
|||
|
TE |
|
|
|
|
|
|
|
TC |
||||
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT161
|
|
|
|
|
INPUTS |
|
|
|
|
|
OUTPUTS |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OPERATING MODE |
|
|
|
CP |
PE |
TE |
|
|
|
|
Pn |
Qn |
TC |
|
MR |
SPE |
|||||||||||
Reset (Clear) |
|
L |
X |
X |
X |
|
X |
|
X |
L |
L |
||
|
|
|
|
|
|
|
|
|
|
|
|
||
Parallel Load |
|
H |
↑ |
X |
X |
|
l |
|
l |
L |
L |
||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
H |
↑ |
X |
X |
|
l |
|
h |
H |
(Note 3) |
||
|
|
|
|
|
|
|
|
|
|
|
|||
Count |
|
H |
↑ |
h |
h |
h (Note 5) |
|
X |
Count |
(Note 3) |
|||
|
|
|
|
|
|
|
|
|
|
|
|||
Inhibit |
|
H |
X |
I (Note 4) |
X |
h (Note 5) |
|
X |
qn |
(Note 3) |
|||
|
|
H |
X |
X |
I (Note 4) |
h (Note 5) |
|
X |
qn |
L |
|||
|
|
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT163 |
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
INPUTS |
|
|
|
|
|
OUTPUTS |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OPERATING MODE |
|
|
|
CP |
PE |
TE |
|
|
|
|
Pn |
Qn |
TC |
|
MR |
|
SPE |
||||||||||
Reset (Clear) |
|
l |
↑ |
X |
X |
|
X |
|
X |
L |
L |
||
|
|
|
|
|
|
|
|
|
|
|
|||
Parallel Load |
h (Note 5) |
↑ |
X |
X |
|
l |
|
l |
L |
L |
|||
|
|
|
|
|
|
|
|
|
|
|
|||
|
h (Note 5) |
↑ |
X |
X |
|
l |
|
h |
H |
(Note 3) |
|||
|
|
|
|
|
|
|
|
|
|
||||
Count |
h (Note 5) |
↑ |
h |
h |
h (Note 5) |
|
X |
Count |
(Note 3) |
||||
|
|
|
|
|
|
|
|
|
|
||||
Inhibit |
h (Note 5) |
X |
I (Note 4) |
X |
h (Note 5) |
|
X |
qn |
(Note 3) |
||||
|
h (Note 5) |
X |
X |
I (Note 4) |
h (Note 5) |
|
X |
qn |
L |
||||
NOTE: H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
3.The TC output is High when TE is High and the counter is at Terminal Count (HHHH for CD74HC/HCT161 and CD74HC/HCT163).
4.The High-to-Low transition of PE or TE on the CD74HC/HCT161 and the CD74HC/HCT163 should only occur while CP is HIGH for conventional operation.
5.The Low-to-High transition of SPE on the CD74HC/HCT161 and SPE or MR on the CD74HC/HCT163 should only occur while CP is HIGH for conventional operation.
2
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . |
-0.5V to 7V |
DC Input Diode Current, IIK |
±20mA |
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . |
|
DC Output Diode Current, IOK |
±20mA |
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . |
|
DC Drain Current, per Output, IO |
±25mA |
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . |
|
DC Output Source or Sink Current per Output Pin, IO |
±25mA |
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . |
|
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . |
. . . .±50mA |
Thermal Information |
|
Thermal Resistance (Typical, Note 6) |
θJA (oC/W) |
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 90 |
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 160 |
Maximum Junction Temperature . . . . . . . . . . . . . . . . |
. . . . . . . 150oC |
Maximum Storage Temperature Range . . . . . . . . . . |
-65oC to 150oC |
Maximum Lead Temperature (Soldering 10s) . . . . . . |
. . . . . . . 300oC |
(SOIC - Lead Tips Only) |
|
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
6. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
|
|
TEST |
|
|
25oC |
|
-40oC TO 85oC |
-55oC TO 125oC |
|
|||
|
|
CONDITIONS |
VCC |
|
|
|
||||||
PARAMETER |
SYMBOL |
VI (V) |
IO (mA) |
(V) |
MIN |
TYP |
MAX |
MIN |
MAX |
MIN |
MAX |
UNITS |
HC TYPES |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
High Level Input |
VIH |
- |
- |
2 |
1.5 |
- |
- |
1.5 |
- |
1.5 |
- |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4.5 |
3.15 |
- |
- |
3.15 |
- |
3.15 |
- |
V |
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6 |
4.2 |
- |
- |
4.2 |
- |
4.2 |
- |
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
Low Level Input |
VIL |
- |
- |
2 |
- |
- |
0.5 |
- |
0.5 |
- |
0.5 |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4.5 |
- |
- |
1.35 |
- |
1.35 |
- |
1.35 |
V |
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6 |
- |
- |
1.8 |
- |
1.8 |
- |
1.8 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
High Level Output |
VOH |
VIH or VIL |
-0.02 |
2 |
1.9 |
- |
- |
1.9 |
- |
1.9 |
- |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-0.02 |
4.5 |
4.4 |
- |
- |
4.4 |
- |
4.4 |
- |
V |
|
CMOS Loads |
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-0.02 |
6 |
5.9 |
- |
- |
5.9 |
- |
5.9 |
- |
V |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
High Level Output |
|
|
- |
- |
- |
- |
- |
- |
- |
- |
- |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-4 |
4.5 |
3.98 |
- |
- |
3.84 |
- |
3.7 |
- |
V |
|
TTL Loads |
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-5.2 |
6 |
5.48 |
- |
- |
5.34 |
- |
5.2 |
- |
V |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Low Level Output |
VOL |
VIH or VIL |
0.02 |
2 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0.02 |
4.5 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
|
CMOS Loads |
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0.02 |
6 |
- |
- |
0.1 |
- |
0.1 |
- |
0.1 |
V |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Low Level Output |
|
|
- |
- |
- |
- |
- |
- |
- |
- |
- |
V |
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4 |
4.5 |
- |
- |
0.26 |
- |
0.33 |
- |
0.4 |
V |
|
TTL Loads |
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5.2 |
6 |
- |
- |
0.26 |
- |
0.33 |
- |
0.4 |
V |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Leakage |
II |
VCC or |
- |
6 |
- |
- |
±0.1 |
- |
±1 |
- |
±1 |
µA |
Current |
|
GND |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3
Loading...