Texas Instruments CD74HCT139M96, CD74HCT139M, CD74HCT139E, CD74HC139M96, CD74HC139M Datasheet
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Data sheet acquired from Harris Semiconductor SCHS148A
September 1997 - Revised May 1999
CD74HC139,
CD74HCT139
High-Speed CMOS Logic
Dual 2-to-4 Line Decoder/Demultiplexer
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Features |
Description |
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Multifunction Capability |
The CD74HC139 and CD74HCT139 devices contain two |
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[ /Title |
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- Binary to 1 of 4 Decoders or 1 to 4 Line |
independent binary to one of four decoders each with a |
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Demultiplexer |
single active low enable input |
(1E |
or |
2E) |
. Data on the select |
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(CD74 |
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Active Low Mutually Exclusive Outputs |
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four |
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HC139 |
normally high outputs to go low. |
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Fanout (Over Temperature Range) |
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If the enable input is high all four outputs remain high. For |
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- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads |
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CD74 |
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demultiplexer operation the enable input is the data input. |
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- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads |
The enable input also functions as a chip select when these |
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HCT13 |
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• Wide Operating Temperature Range . . . -55oC to 125oC |
devices are cascaded. This device is functionally the same |
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9) |
as the CD4556B and is pin compatible with it. |
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/Sub- |
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Balanced Propagation Delay and Transition Times |
The outputs of these devices can drive 10 low power |
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ject |
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Significant Power Reduction Compared to LSTTL |
Schottky TTL equivalent loads. The 74HCT logic family is |
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(High |
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Logic ICs |
functionally as well as pin equivalent to the 74LS logic family. |
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Speed |
• HC Types |
Ordering Information |
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CMOS |
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- 2V to 6V Operation |
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Logic |
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- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at |
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TEMP. RANGE (oC) |
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PKG. |
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Dual |
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VCC = 5V |
PART NUMBER |
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PACKAGE |
NO. |
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2-to-4 |
• HCT Types |
CD74HC139E |
-55 to 125 |
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16 Ld PDIP |
E16.3 |
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Line |
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- 4.5V to 5.5V Operation |
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CD74HCT139E |
-55 to 125 |
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16 Ld PDIP |
E16.3 |
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Decod |
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- Direct LSTTL Input Logic Compatibility, |
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CD74HC139M |
-55 to 125 |
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16 Ld SOIC |
M16.15 |
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VIL= 0.8V (Max), VIH = 2V (Min) |
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- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH |
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CD74HCT139M |
-55 to 125 |
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16 Ld SOIC |
M16.15 |
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Memory Decoding, Data Routing, Code Conversion |
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NOTES: |
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1. When ordering, use the entire part number. Add the suffix 96 to |
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obtain the variant in the tape and reel. |
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2. Die is available which meets all electrical specifications. Please |
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contact your local sales office or customer service for ordering |
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information. |
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Pinout
CD74HC139, CD74HCT139
(PDIP, SOIC)
TOP VIEW
1E |
1 |
16 VCC |
1A0 |
2 |
15 |
2E |
1A1 |
3 |
14 |
2A0 |
1Y0 |
4 |
13 |
2A1 |
1Y1 |
5 |
12 |
2Y0 |
1Y2 |
6 |
11 |
2Y1 |
1Y3 |
7 |
10 |
2Y2 |
GND |
8 |
9 |
2Y3 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Texas Instruments Incorporated 1999
1
CD74HC139, CD74HCT139
Functional Diagram
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4 |
(12) |
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2 (14) |
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Y0 |
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5 |
(11) |
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A0 |
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Y1 |
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3 (13) |
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6 |
(10) |
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Y2 |
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A1 |
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7 |
(9) |
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1 |
(15) |
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Y3 |
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E |
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TRUTH TABLE
INPUTS ENABLE SELECT |
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OUTPUTS |
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A1 |
A0 |
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E |
Y3 |
Y2 |
Y1 |
Y0 |
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0 |
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0 |
0 |
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1 |
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1 |
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1 |
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0 |
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0 |
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1 |
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1 |
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1 |
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0 |
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1 |
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0 |
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1 |
0 |
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1 |
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0 |
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0 |
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1 |
1 |
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1 |
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1 |
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1 |
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X |
X |
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1 |
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1 |
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1 |
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1 |
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NOTE: X = Don’t Care, Logic 1 = High, Logic 0 = Low
Logic Diagram
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4 (12) |
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2 (14) |
Y0 |
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A0 |
5 (11) |
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3 (13) |
Y1 |
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A1 |
6 (10) |
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Y2 |
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1 (15) |
7 (9) |
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Y3 |
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E |
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