Texas Instruments CD74HCT125M96, CD74HCT125M, CD74HCT125E, CD74HC125M96, CD74HC125M Datasheet

[ /Title (CD74 HC125

,

CD74

HCT12

5) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState)

Data sheet acquired from Harris Semiconductor SCHS143

November 1997

CD74HC125,

CD74HCT125

High Speed CMOS Logic

Quad Buffer, Three-State

Features

•Three-State Outputs

•Separate Output Enable Inputs

•Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The Harris CD74HC125 and CD74HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when “HIGH” puts the output in the high impedance state

Ordering Information

	TEMP. RANGE		PKG.
PART NUMBER	(oC)	PACKAGE	NO.
CD74HC125E	-55 to 125	14 Ld PDIP	E14.3
CD74HCT125E	-55 to 125	14 Ld PDIP	E14.3
CD74HC125M	-55 to 125	14 Ld SOIC	M14.15
CD74HCT125M	-55 to 125	14 Ld SOIC	M14.15
NOTES:

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Pinout

CD74HC125, CD74HCT125

(PDIP, SOIC)

TOP VIEW

1OE			1		14	VCC
	1A
			2		13	4OE
	1Y					4A
			3		12
						4Y
2OE			4		11
	2A
			5		10	3OE
	2Y					3A
			6		9
GND						3Y
			7		8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1771.1
Copyright © Harris Corporation 1997	1

CD74HC125, CD74HCT125

Functional Diagram

1
1OE
2	3	1Y
1A
4
2OE
5	6	2Y
2A
10
3OE
9	8	3Y
3A
13
4OE
12	11	4Y
4A
	GND = 7
	VCC = 14

TRUTH TABLE

INPUTS			OUTPUTS
nA		nOE	nY
H		L	H
L		L	L
X		H	Z

NOTE:

H = High Voltage Level

L = Low Voltage Level

X = Don’t Care

Z = High Impedance, OFF State

Logic Diagram

	P
nA	nY
	n
nOE

2

CD74HC125, CD74HCT125

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±35mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±70mA

Thermal Information
Thermal Resistance (Typical, Note 3)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 175
Maximum Junction Temperature . . . . . . . . . . . . . . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
Voltage
			-7.8	6	5.48	-	-	5.34	-	5.2	-	V
TTL Loads
Low Level Output	VOL	VIH or	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage		VIL
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			6	4.5	-	-	0.26	-	0.33	-	0.4	V
Voltage
			7.8	6	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	μA
Current		GND

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