Texas Instruments CD74FCT573SM96, CD74FCT573SM, CD74FCT573M96, CD74FCT573M, CD74FCT573E Datasheet
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CD74FCT573AT was not acquired from Harris Semiconductor.
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CD74FCT573, |
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Data sheet acquired from Harris Semiconductor |
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CD74FCT573AT |
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SCHS260A |
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BiCMOS FCT Interface Logic, |
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January 1997 |
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RECOMMENDED |
Octal Transparent Latches, Three-State |
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NOT |
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Features |
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NEW |
DESIGNS |
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Description |
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FOR |
Technology |
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CMOS |
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• Buffered Inputs |
Use |
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The CD74FCT573 and CD74FCT573AT octal transparent |
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• Typical Propagation Delay: 3.9ns at VCC = 5V, |
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latches use a small geometry BiCMOS technology. The out- |
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TA = 25oC, CL = 50pF (CD74FCT573AT) |
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put stage is a combination of bipolar and CMOS transistors |
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• SCR Latchup Resistant BiCMOS Process and |
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that limits the output HIGH level to two diode drops below |
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VCC. This resultant lowering of output swing (0V to 3.7V) |
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Circuit Design |
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• FCTXXX Types |
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reduces power bus ringing (a source of EMI) and minimizes |
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VCC bounce and ground bounce and their effects during |
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- Speed of Bipolar FAST™/AS/S |
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simultaneous output switching. The output configuration |
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• FCTXXXAT Types |
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also enhances switching speed and is capable of sinking |
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48 milliamperes. |
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- 30% Faster than FAST™/AS/S with Significantly |
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Reduced Power Consumption |
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The CD74FCT573 and CD74FCT573AT outputs are trans- |
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• 48mA Output Sink Current |
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parent to the inputs when the Latch Enable |
(LE) |
is HIGH. |
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When the Latch Enable (LE) goes LOW, the data is latched. |
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• Output Voltage Swing Limited to 3.7V at VCC = 5V |
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The Output Enable |
(OE) |
controls the three-state outputs. |
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• Controlled Output Edge Rates |
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When the Output Enable |
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is HIGH, the outputs are in |
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(OE) |
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• Input/Output Isolation to VCC |
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the high impedance state. The latch operation is indepen- |
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• BiCMOS Technology with Low Quiescent Power |
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dent of the state of the Output Enable. |
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Ordering Information |
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TEMP. |
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PKG. |
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PART NUMBER |
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RANGE (oC) |
PACKAGE |
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NO. |
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CD74FCT573ATE |
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0 to 70 |
20 Ld PDIP |
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E20.3 |
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CD74FCT573M |
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0 to 70 |
20 Ld SOIC |
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M20.3 |
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CD74FCT573SM |
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0 to 70 |
20 Ld SSOP |
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M20.209 |
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NOTE: When ordering the suffix M and SM packages, use the entire |
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part number. Add the suffix 96 to obtain the variant in the tape and reel. |
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Pinout
CD74FCT573, CD74FCT573AT
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(PDIP, SOIC, SSOP) |
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TOP VIEW |
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OE |
1 |
20 |
VCC |
D0 |
2 |
19 |
Q0 |
D1 |
3 |
18 |
Q1 |
D2 |
4 |
17 |
Q2 |
D3 |
5 |
16 |
Q3 |
D4 |
6 |
15 |
Q4 |
D5 |
7 |
14 |
Q5 |
D6 |
8 |
13 |
Q6 |
D7 |
9 |
12 |
Q7 |
GND |
10 |
11 LE |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 2304.2 |
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FAST™ is a trademark of Fairchild Semiconductor. |
8-1 |
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Copyright © Harris Corporation 1997 |
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CD74FCT573, CD74FCT573AT
Functional Diagram
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D0 |
2 |
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19 |
Q0 |
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3 |
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18 |
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D1 |
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Q1 |
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4 |
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17 |
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D2 |
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Q2 |
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5 |
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16 |
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D3 |
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Q3 |
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6 |
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15 |
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D4 |
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Q4 |
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7 |
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14 |
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D5 |
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Q5 |
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8 |
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13 |
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D6 |
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Q6 |
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9 |
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12 |
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D7 |
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Q7 |
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11 |
1 |
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LE |
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GND = PIN 10 |
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OE |
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VCC = PIN 20 |
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TRUTH TABLE (Note 1)
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OUTPUT |
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LATCH |
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ENABLE |
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ENABLE |
DATA |
OUTPUT |
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L |
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H |
H |
H |
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L |
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H |
L |
L |
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L |
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L |
l |
L |
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L |
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L |
h |
H |
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H |
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X |
X |
Z |
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NOTE:
1.H = HIGH Voltage Level L = LOW Voltage Level
l = Low voltage level one set up time prior to the high to low latch enable transition. h = High voltage level one set up time prior to the high to low latch enable transition. X = Irrelevant
Z = High Impedance
IEC Logic Symbol
CD74FCT573, CD74FCT573AT
1 |
EN |
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11 |
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C1 |
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2 |
1D |
19 |
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3 |
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18 |
4 |
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17 |
5 |
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16 |
6 |
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15 |
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7 |
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14 |
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8 |
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13 |
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9 |
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12 |
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8-2
CD74FCT573, CD74FCT573AT
Absolute Maximum Ratings
DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
Thermal Information |
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Thermal Resistance (Typical, Note 2) |
θJA (oC/W) |
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 135 |
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 125 |
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 130 |
Maximum Junction Temperature . . . . . . . . . . . . . . . . |
. . . . . . . 150oC |
Maximum Storage Temperature Range . . . . . . . . . . |
-65oC to 150oC |
Maximum Lead Temperature (Soldering 10s) . . . . . . |
. . . . . . . 300oC |
(SOIC and SSOP-Lead Tips Only) |
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Operating Conditions
Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications |
Commercial Temperature Range 0oC to 70oC, V |
CC |
Max = 5.25V, V |
CC |
Min = 4.75V (Note 5) |
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AMBIENT TEMPERATURE (TA) |
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TEST CONDITIONS |
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25oC |
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0oC TO 70oC |
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PARAMETER |
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SYMBOL |
VI (V) |
IO (mA) |
VCC (V) |
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MIN |
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MAX |
MIN |
MAX |
UNITS |
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High Level Input Voltage |
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VIH |
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4.75 to 5.25 |
2 |
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- |
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2 |
- |
V |
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Low Level Input Voltage |
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VIL |
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4.75 to 5.25 |
- |
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0.8 |
- |
0.8 |
V |
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High Level Output Voltage |
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VOH |
VIH or VIL |
-15 |
Min |
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2.4 |
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- |
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2.4 |
- |
V |
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Low Level Output Voltage |
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VOL |
VIH or VIL |
48 |
Min |
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- |
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0.55 |
- |
0.55 |
V |
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High Level Input Current |
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IIH |
VCC |
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Max |
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- |
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0.1 |
- |
1 |
μA |
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Low Level Input Current |
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IIL |
GND |
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Max |
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- |
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-0.1 |
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-1 |
μA |
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Three-State Leakage Current |
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IOZH |
VCC |
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Max |
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- |
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0.5 |
- |
10 |
μA |
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IOZL |
GND |
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Max |
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- |
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-0.5 |
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-10 |
μA |
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Input Clamp Voltage |
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VIK |
VCC or |
-18 |
Min |
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- |
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-1.2 |
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-1.2 |
V |
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GND |
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Short Circuit Output Current |
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IOS |
VO = 0 |
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Max |
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-60 |
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- |
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-60 |
- |
mA |
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(Note 3) |
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VCC or |
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GND |
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Quiescent Supply Current, |
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ICC |
VCC or |
0 |
Max |
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- |
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8 |
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80 |
μA |
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MSI |
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GND |
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Additional Quiescent Supply |
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ICC |
3.4V |
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Max |
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- |
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1.6 |
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1.6 |
mA |
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Current per Input Pin |
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(Note 4) |
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TTL Inputs High, 1 Unit Load |
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NOTES: |
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3.Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
4.Inputs that are not measured are at VCC or GND.
5. FCT Input Loading: All inputs are 1 unit load. Unit load is ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC.
8-3
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