Texas Instruments CD74HC4050PWR, CD74HC4050M96, CD74HC4050M, CD74HC4050E, CD74HC4049PWR Datasheet

Data sheet acquired from Harris Semiconductor SCHS205A

CD74HC4049,

CD74HC4050

February 1998 - Revised June 1999

High-Speed CMOS Logic

Hex Buffers, Inverting and Non-Inverting

Features

Description

• Typical Propagation Delay: 6ns at VCC = 5V,

The CD74HC4049 and CD74HC4050 are fabricated with

C

L

= 15pF, T = 25oC

high-speed silicon gate technology. They have a modified

[ /Title

A

input protection structure that enables these parts to be

• High-to-Low Voltage Level Converter for up to Vl = 16V

(CD74H

used as logic level translators which convert high-level logic

C4049,

•

Fanout (Over Temperature Range)

to a low-level logic while operating off the low-level logic

CD74H

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

supply. For example, 15-V input pulse levels can be down-

converted

to 0-V

to

5-V logic

levels. The

modified input

C4050)

-

Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

protection

structure

protects

the

input

from

negative

o

o

/Sub-

•

C

electrostatic discharge. These parts also can be used as

Wide Operating Temperature Range . . . –55C to 125

ject

•

Balanced Propagation Delay and Transition Times

simple buffers or

inverters without level translation. The

CD74HC4049 and CD74HC4050 are enhanced versions of

(High

• Significant Power Reduction Compared to LSTTL

equivalent CMOS types.

Speed

Logic ICs

Ordering Information

CMOS

• HC Types

Logic

-

2V to 6V Operation

TEMP. RANGE

PKG.

Hex

- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at

PART NUMBER

o

PACKAGE

NO.

( C)

VCC = 5V

CD74HC4049E

–55 to 125

16 Ld PDIP

E16.3

CD74HC4050E

–55 to 125

16 Ld PDIP

E16.3

CD74HC4049M

–55 to 125

16 Ld SOIC

M16.15

CD74HC4050M

–55 to 125

16 Ld SOIC

M16.15

CD74HC4050PW

–55 to 125

16 Ld TSSOP

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

the M suffix or the R suffix to the PW package to obtain the

variant in the tape and reel.

2. Wafer and die is available which meets all electrical

specifications. Please contact your local sales office or

customer service for ordering information.

Pinout

	CD74HC4049, CD74HC4050
		(PDIP, SOIC, TSSOP)
			TOP VIEW
4049	4050			4050	4049
VCC	VCC	1	16	NC	NC
1Y	1Y	2	15	6Y	6Y
1A	1A	3	14	6A	6A
2Y	2Y	4	13	NC	NC
2A	2A	5	12	5Y	5Y
3Y	3Y	6	11	5A	5A
3A	3A	7	10	4Y	4Y
GND	GND	8	9	4A	4A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright © 1999 Texas Instruments Incorporated

1

CD74HC4049, CD74HC4050

Functional Diagram

4050	4049	1
	VCC
		2
1Y	1Y
		3
	1A
		4
2Y	2Y
	2A	5
3Y	3Y	6
	3A	7
		8
	GND

16	4049	4050
	NC
15	6Y	6Y
14	6A
13	NC	NC
12	5Y
11	5A	5Y
10	4Y
9	4A

Logic Diagrams

	HC4049		HC4050
A	Y	A	Y

2