Data sheet acquired from Harris Semiconductor SCHS197
August 1997
CD74HC4002
High Speed CMOS Logic
Dual 4-Input NOR Gate
[ /Title (CD74H C4002) /Subject (High Speed CMOS Logic Dual 4- Input NOR Gate)
Features
•Typical Propagation Delay = 8ns at VCC = 5V, CL = 15pF, TA = 25oC
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
Description
The CD74HC4002 logic gate utilizes silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The CD74HC4002 logic family is functional as well as pin compatible with the standard 74LS logic family.
Ordering Information
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TEMP. RANGE (oC) |
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PKG. |
PART NUMBER |
PACKAGE |
NO. |
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CD74HC4002E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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CD74HC4002M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
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NOTES: |
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1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2.Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
Pinout
CD74HC4002 (PDIP, SOIC)
TOP VIEW
1Y |
1 |
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14 |
VCC |
1A |
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2Y |
2 |
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13 |
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1B |
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2D |
3 |
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12 |
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1C |
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2C |
4 |
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11 |
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1D |
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2B |
5 |
|
10 |
||
NC |
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2A |
6 |
|
9 |
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GND |
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NC |
7 |
|
8 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1776.1 |
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Copyright © Harris Corporation 1997 |
1 |
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CD74HC4002
Functional Diagram
2
1A
3
1B
4
1C
5
1D
9
2A
10
2B
11
2C
12
2D
1
1Y
13
2Y
GND = 7 VCC = 14 NC = 6, 8
TRUTH TABLE
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INPUTS |
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OUTPUT |
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nA |
nB |
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nC |
nD |
nY |
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L |
L |
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L |
L |
H |
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H |
X |
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X |
X |
L |
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X |
H |
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X |
X |
L |
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X |
X |
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H |
X |
L |
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X |
X |
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X |
H |
L |
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NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Symbol
nA nB
nY
nC nD
2
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