Texas Instruments CD74FCT574SM, CD74FCT574M96, CD74FCT574M, CD74FCT574E, CD74FCT564M Datasheet
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Data sheet acquired from Harris Semiconductor
SCHS259
January 1997 |
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RECOMMENDED |
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CMOS |
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•Buffered Inputs
•Typical Propagation Delay: 5.6ns at VCC = 5V, TA = 25oC
•Positive Edge Triggered
•CD74FCT564
-Inverting
•CD74FCT574
-Noninverting
•SCR Latchup Resistant BiCMOS Process and Circuit Design
•Speed of Bipolar FAST™/AS/S
•48mA Output Sink Current
•Output Voltage Swing Limited to 3.7V at VCC = 5V
•Controlled Output Edge Rates
•Input/Output Isolation to VCC
•BiCMOS Technology with Low Quiescent Power
CD74FCT564,
CD74FCT574
BiCMOS FCT Interface Logic,
Octal D-Type Flip-Flops, Three-State
Description
The CD74FCT564 and CD74FCT574 are octal D-Type, three-state, positive edge triggered flip-flops which use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 milliamperes.
The eight flip-flops enter data into their registers on the LOW to HIGH transition of the clock (CP). The Output Enable (OE) controls the three state outputs and is independent of the register operation. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The CD74FCT564 and CD74FCT574 share the same configurations; the CD74FCT564, however, has inverted outputs and the CD74FCT574 has noninverted outputs.
Ordering Information
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TEMP. |
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PKG. |
PART NUMBER |
RANGE (oC) |
PACKAGE |
NO. |
CD74FCT564E |
0 to 70 |
20 Ld PDIP |
E20.3 |
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CD74FCT574E |
0 to 70 |
20 Ld PDIP |
E20.3 |
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CD74FCT564M |
0 to 70 |
20 Ld SOIC |
M20.3 |
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CD74FCT574M |
0 to 70 |
20 Ld SOIC |
M20.3 |
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CD74FCT574SM |
0 to 70 |
20 Ld SSOP |
M20.209 |
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NOTE: When ordering the suffix M and SM packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinouts
CD74FCT564 |
CD74FCT574 |
(PDIP, SOIC, SSOP) |
(PDIP, SOIC, SSOP) |
TOP VIEW |
TOP VIEW |
OE |
1 |
20 |
VCC |
D0 |
2 |
19 |
Q0 |
D1 |
3 |
18 |
Q1 |
D2 |
4 |
17 |
Q2 |
D3 |
5 |
16 |
Q3 |
D4 |
6 |
15 |
Q4 |
D5 |
7 |
14 |
Q5 |
D6 |
8 |
13 |
Q6 |
D7 |
9 |
12 |
Q7 |
GND |
10 |
11 CP |
OE |
1 |
20 |
VCC |
D0 |
2 |
19 |
Q0 |
D1 |
3 |
18 |
Q1 |
D2 |
4 |
17 |
Q2 |
D3 |
5 |
16 |
Q3 |
D4 |
6 |
15 |
Q4 |
D5 |
7 |
14 |
Q5 |
D6 |
8 |
13 |
Q6 |
D7 |
9 |
12 |
Q7 |
GND |
10 |
11 CP |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 2295.2 |
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FAST™ is a trademark of Fairchild Semiconductor. |
8-1 |
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Copyright © Harris Corporation 1997 |
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CD74FCT564, CD74FCT574
Functional Diagram
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2 |
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19 |
CD74FCT574 |
CD74FCT564 |
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D0 |
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Q0 |
Q0 |
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3 |
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18 |
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D1 |
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Q1 |
Q1 |
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4 |
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17 |
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D2 |
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Q2 |
Q2 |
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5 |
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16 |
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D3 |
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Q3 |
Q3 |
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6 |
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15 |
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D4 |
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Q4 |
Q4 |
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7 |
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14 |
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D5 |
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Q5 |
Q5 |
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8 |
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13 |
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D6 |
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Q6 |
Q6 |
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9 |
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12 |
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D7 |
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Q7 |
Q7 |
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1 |
11 |
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OE |
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GND = PIN 10 |
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CP |
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VCC = PIN 20 |
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TRUTH TABLE (NOTE 1)
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OUTPUTS |
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INPUTS |
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CD74FCT564 |
CD74FCT574 |
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CP |
DN |
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QN |
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OE |
QN |
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L |
− |
H |
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L |
H |
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L |
− |
L |
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H |
L |
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L |
L |
X |
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Qo |
Qo |
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H |
X |
X |
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Z |
Z |
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NOTE:
1. H = High Level (Steady State) L = Low Level (Steady State) X = Don't Care
− = Transition from low to high level
Qo = The level of Q before the indicated steady state input conditions were established.
Z = HIGH Impedance
IEC Logic Symbols
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CD74FCT564 |
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CD74FCT574 |
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1 |
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EN |
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1 |
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EN |
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11 |
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11 |
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>C1 |
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>C1 |
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2 |
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1D |
19 |
2 |
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1D |
19 |
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3 |
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18 |
3 |
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18 |
4 |
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17 |
4 |
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17 |
5 |
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16 |
5 |
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16 |
6 |
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15 |
6 |
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15 |
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7 |
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14 |
7 |
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14 |
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8 |
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13 |
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9 |
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12 |
9 |
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12 |
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8-2
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