Texas Instruments CD74HCT02M96, CD74HCT02M, CD74HCT02E, CD74HC02M96, CD74HC02M Datasheet

Data sheet acquired from Harris Semiconductor SCHS125

March 1998

CD74HC02,

CD74HCT02

High Speed CMOS Logic

Quad Two-Input NOR Gate

[ /Title (CD74H C02, CD74H CT02) /Subject (High Speed CMOS Logic Quad Two-

Features

•Buffered Inputs

•Typical Propagation Delay: 7ns at VCC = 5V, CL = 15pF, TA = 25oC

•Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

•Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

•Related Literature

-CD54HC02F3A and CD54HCT02F3A Military Data Sheet, Document Number 3754

Description

The Harris CD74HC02, CH74HCT02 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is

Pinout

CD74HC02, CD74HCT02

(PDIP, SOIC)

TOP VIEW

1Y	1		14	VCC
1A				4Y
	2		13
1B				4B
	3		12
2Y				4A
	4		11
2A				3Y
	5		10
2B				3B
	6		9
GND				3A
	7		8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1647.1
Copyright © Harris Corporation 1998	1

CD74HC02, CD74HCT02

Functional Diagram

	1	14
	1Y	VCC
	2	13
	1A	4Y
	3	12
	1B	4B
	4	11
	2Y	4A
	5	10
	2A	3Y
	6	9
	2B	3B
	7	8
	GND	3A
	TRUTH TABLE
	INPUTS	OUTPUT
nA	nB	nY
L	L	H
L	H	L
H	L	L
H	H	L

NOTE: H = High Voltage Level, L = Low Voltage Level

Logic Diagram

nA

nB

2