Texas Instruments CD74HCT03M96, CD74HCT03M, CD74HCT03E, CD74HC03M96, CD74HC03M Datasheet
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Data sheet acquired from Harris Semiconductor SCHS126
February 1998
CD74HC03,
CD74HCT03
High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain
[ /Title (CD74H C03, CD74H CT03) /Subject (High Speed CMOS Logic Quad 2- Input
Features
•Buffered Inputs
•Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC
•Output Pull-up to 10V
•Fanout (Over Temperature Range)
-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
•Wide Operating Temperature Range . . . -55oC to 125oC
•Balanced Propagation Delay and Transition Times
•Significant Power Reduction Compared to LSTTL Logic ICs
•HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
•HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH
Description
The Harris CD74HC03 and CD74HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally as well as pin compatible with the standard 74LS logic family.
These open drain NAND gates can drive into resistive loads to output voltages as high as 10V. Minimum values of RL required verses load voltage are shown in Figure 2.
Ordering Information
|
TEMP. RANGE |
|
PKG. |
PART NUMBER |
(oC) |
PACKAGE |
NO. |
CD74HC03E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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|
|
|
CD74HCT03E |
-55 to 125 |
14 Ld PDIP |
E14.3 |
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|
|
CD74HC03M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
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|
|
CD74HCT03M |
-55 to 125 |
14 Ld SOIC |
M14.15 |
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NOTES: |
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1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2.Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
Pinout
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
1A |
1 |
|
14 |
VCC |
1B |
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|
4B |
2 |
|
13 |
||
1Y |
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4A |
3 |
|
12 |
||
2A |
|
|
|
4Y |
4 |
|
11 |
||
2B |
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|
3B |
5 |
|
10 |
||
2Y |
|
|
|
3A |
6 |
|
9 |
||
GND |
|
|
|
3Y |
7 |
|
8 |
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. |
File Number 1832.1 |
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Copyright © Harris Corporation 1998 |
1 |
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CD74HC03, CD74HCT03
Functional Diagram
1A |
1 |
3 |
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2 |
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1B |
1Y |
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2A |
4 |
6 |
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5 |
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2B |
2Y |
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3A |
9 |
8 |
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10 |
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3B |
3Y |
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4A |
12 |
11 |
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13 |
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4B |
4Y |
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GND = 7 |
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VCC = 14 |
TRUTH TABLE
A |
B |
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Y |
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L |
L |
Z (Note 4) |
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H (Note 3) |
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H |
L |
Z (Note 4) |
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H (Note 3) |
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L |
H |
Z (Note 4) |
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H (Note 3) |
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H |
H |
L |
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L |
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NOTES:
3.Requires pull-up (RL to VL)
4.Without pull-up (high impedance)
Logic Symbol
nA 
nY
nB 
2
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