Texas Instruments CD74HCT04M96, CD74HCT04M, CD74HCT04E, CD74HC04M96, CD74HC04M Datasheet

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Data sheet acquired from Harris Semiconductor SCHS117

August 1997

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

High Speed CMOS Logic Hex Inverter

[ /Title (CD54H C04, CD54H CT04, CD74H C04, CD74H CT04) /Subject (High Speed

Features

Buffered Inputs

Typical Propagation Delay: 6ns at VCC = 5V, CL = 15pF, TA = 25oC

Fanout (Over Temperature Range)

-Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Wide Operating Temperature Range . . . -55oC to 125oC

Balanced Propagation Delay and Transition Times

Significant Power Reduction Compared to LSTTL Logic ICs

HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il 1μA at VOL, VOH

Description

The Harris CD54HC04, CD54HCT04, CD74HC04 and CD74HCT04 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

Ordering Information

 

TEMP. RANGE

 

PKG.

PART NUMBER

(oC)

PACKAGE

NO.

CD74HC04E

-55 to 125

14 Ld PDIP

E14.3

 

 

 

 

CD74HCT04E

-55 to 125

14 Ld PDIP

E14.3

 

 

 

 

CD74HC04M

-55 to 125

14 Ld SOIC

M14.15

 

 

 

 

CD74HCT04M

-55 to 125

14 Ld SOIC

M14.15

 

 

 

 

CD54HC04F

-55 to 125

14 Ld CERDIP

F14.3

 

 

 

 

CD54HCT04F

-55 to 125

14 Ld CERDIP

F14.3

 

 

 

 

CD54HC04W

-55 to 125

Wafer

 

 

 

 

 

CD54HCT04W

-55 to 125

Wafer

 

 

 

 

 

CD54HC04H

-55 to 125

Die

 

 

 

 

 

CD54HCT04H

-55 to 125

Die

 

 

 

 

 

NOTE:

 

 

 

1.When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

Pinout

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

(PDIP, CERDIP, SOIC)

TOP VIEW

1A

1

 

14

VCC

 

 

 

 

 

 

6A

 

1Y

 

2

 

13

2A

 

 

 

 

 

 

3

 

12

 

6Y

 

 

 

 

 

 

 

5A

 

2Y

 

4

 

11

3A

 

 

 

 

 

 

5

 

10

 

5Y

 

 

 

 

 

 

 

4A

 

3Y

 

6

 

9

GND

 

 

 

 

 

 

7

 

8

 

4Y

 

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1471.1

 

Copyright © Harris Corporation 1997

1

 

 

 

Texas Instruments CD74HCT04M96, CD74HCT04M, CD74HCT04E, CD74HC04M96, CD74HC04M Datasheet

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

Functional Diagram

1

1A

2

1Y

3

2A

4

2Y

5

3A

6

3Y

7

GND

14

VCC

13

6A

12

6Y

11

5A

10

5Y

9

4A

8

4Y

 

TRUTH TABLE

 

 

 

INPUTS

 

 

 

nA

 

nY

 

 

 

L

 

H

 

 

 

H

 

L

 

 

 

NOTE: H = High Voltage Level, L = Low Voltage Level

Logic Symbol

nA

nY

2

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