Motorola MC10E142FN, MC100E142FNR2, MC100E142FN, MC10E142FNR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

9 Bit Shift Register

The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 ± D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

•700MHz Min. Shift Frequency

•9-Bit for Byte-Parity Applications

•Asynchronous Master Reset

•Dual Clocks

•Extended 100E VEE Range of ± 4.2V to ± 5.46V

•75kΩ Input Pulldown Resistors

The SEL (Select) input pin is used to switch between the two modes of operation Ð SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.

SEL

D8

D7

D6

D5

VCCO

Q8

MR

25

24

23

22

21

20

19

26

18

Q7

CLK1

27

17

Q6

CLK2

28

16

VCC

VEE

1

Pinout: 28-Lead PLCC

15

Q5

(Top View)

S-IN

2

14

VCCO

D0

3

13

Q4

D1

4

12

Q3

5

6

7

8

9

10

11

D2

D3

D4

VCCO

Q0

Q1

Q2

* All VCC and VCCO pins are tied together on the die.

PIN NAMES

Pin

Function

D0 ± D8

Parallel Data Inputs

S-IN

Serial Data Input

SEL

Mode Select Input

CLK1, CLK2

Clock Inputs

MR

Master Reset

Q0 ± Q8

Data Outputs

FUNCTIONS

SEL

Mode

L

Load

H

Shift

MC10E142

MC100E142

9-BIT SHIFT REGISTER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

		LOGIC DIAGRAM
	S-IN
		1	D	Q	Q0
	D0	0
		1	D	Q	Q1
	D1	0
	D2	1	D	Q	Q2
		0
		1	D	Q	Q3
	D3	0
		1	D	Q	Q8
	D8	0
	SEL
	CLK1
	CLK2
	MR

12/93

Motorola, Inc. 1996

REV 2

MC10E142 MC100E142

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)

		0°C			25°C			85°C
Symbol	Characteristic	min typ	max	min	typ	max	min	typ	max	Unit	Condition
IIH	Input HIGH Current		150			150			150	μA
IEE	Power Supply Current									mA
	10E	120	145		120	145		120	145
	100E	120	145		120	145		138	165

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)

			0°C			25°C			85°C
Symbol	Characteristic	min	typ	max	min	typ	max	min	typ	max	Unit	Condition
fSHIFT	Max. Shift Frequency	700	900		700	900		700	900		MH
											z
tPLH	Propagation Delay to Output										ps
tPHL	Clk	600	800	1000	600	800	1000	600	800	1000
	MR	600	800	1000	600	800	1000	600	800	1000
ts	Setup Time										ps
	D	50	±100		50	±100		50	±100
	SEL	300	150		300	150		300	150
th	Hold Time										ps
	D	300	100		300	100		300	100
	SEL	75	±150		75	±150		75	±150
tRR	Reset Recovery Time	900	700		900	700		900	700		ps
tPW	Minimum Pulse Width										ps
	Clk, MR	400			400			400
tSKEW	Within-Device Skew		75			75			75		ps	Note 1
tr	Rise/Fall Times										ps
tf	20 - 80%	300	525	800	300	525	800	300	525	800

1. Within-device skew is defined as identical transitions on similar paths through a device.

MOTOROLA

2±2