MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input Multiplexer/
Latch
The MC10173 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information.
PD = 275 mW typ/pkg (No Load)
tpd = 2.5 ns typ
tr, tf = 2.0 ns typ (20%±80%)
LOGIC DIAGRAM
SELECT 9 |
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D00 |
6 |
1 Q0 |
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D01 |
5 |
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D10 |
4 |
2 Q1 |
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D11 |
3 |
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D20 13 |
15 Q2 |
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D21 12 |
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D30 11 |
14 Q3 |
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D31 10 |
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CLOCK 7 |
VCC = PIN 16 |
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VEE = PIN 8 |
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TRUTH TABLE
SELECT |
CLOCK |
Q0n+1 |
H |
L |
D00 |
L |
L |
D01 |
X |
H |
Q0n |
MC10173
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
Q0 |
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1 |
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16 |
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VCC |
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Q1 |
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2 |
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15 |
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Q2 |
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D11 |
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3 |
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14 |
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Q3 |
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D10 |
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4 |
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13 |
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D20 |
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D01 |
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5 |
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12 |
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D21 |
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D00 |
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6 |
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11 |
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D30 |
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D31 |
CLOCK |
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7 |
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10 |
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VEE |
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8 |
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9 |
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SELECT |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
3±117 |
REV 5 |
MC10173
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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73 |
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66 |
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73 |
mAdc |
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Input Current |
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IinH |
5 |
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470 |
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295 |
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295 |
μAdc |
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6 |
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470 |
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295 |
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295 |
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7 |
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400 |
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250 |
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250 |
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9 |
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400 |
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250 |
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250 |
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IinL |
All |
0.5 |
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0.5 |
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0.3 |
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μAdc |
Output Voltage |
Logic 1 |
VOH |
1 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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2 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
Logic 0 |
VOL |
1 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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2 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
1 |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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2 |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
1 |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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2 |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
(50Ω Load) |
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ns |
Propagation |
Data Input |
t6+1+ |
1 |
0.8 |
3.7 |
1.0 |
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2.5 |
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3.5 |
1.1 |
5.3 |
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Delay |
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t6±1± |
1 |
0.8 |
3.7 |
1.0 |
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2.5 |
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3.5 |
1.1 |
5.3 |
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t5+1+ |
1 |
0.8 |
3.7 |
1.0 |
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2.5 |
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3.5 |
1.1 |
5.3 |
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t5±1± |
1 |
0.8 |
3.7 |
1.0 |
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2.5 |
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3.5 |
1.1 |
5.3 |
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Clock Input |
t7±1+ |
1 |
1.6 |
7.2 |
1.6 |
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4.5 |
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6.8 |
1.4 |
6.8 |
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t7±1± |
1 |
1.6 |
7.2 |
1.6 |
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4.5 |
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6.8 |
1.4 |
6.8 |
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Select Input |
t9+1+ |
1 |
1.1 |
6.2 |
1.3 |
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3.5 |
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5.7 |
1.2 |
6.7 |
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t9+1± |
1 |
1.1 |
6.2 |
1.3 |
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3.5 |
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5.7 |
1.2 |
6.7 |
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t9±1+ |
1 |
1.1 |
6.2 |
1.3 |
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3.5 |
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5.7 |
1.2 |
6.7 |
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t9±1± |
1 |
1.1 |
6.2 |
1.3 |
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3.5 |
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5.7 |
1.2 |
6.7 |
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Setup TIme |
Data Input |
tsetup |
1 |
2.0 |
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2.0 |
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1.5 |
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2.0 |
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Select Input |
tsetup |
1 |
3.0 |
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3.0 |
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2.5 |
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3.0 |
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Hold TIme |
Data Input |
thold |
1 |
2.5 |
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2.5 |
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0.0 |
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2.5 |
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Select Input |
thold |
1 |
1.5 |
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1.5 |
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±0.5 |
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1.5 |
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Rise Time |
(20 to 80%) |
t+ |
1 |
1.2 |
4.0 |
1.5 |
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2.0 |
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3.5 |
1.4 |
4.0 |
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Fall Time |
(20 to 80%) |
t± |
1 |
1.2 |
4.0 |
1.5 |
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2.0 |
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3.5 |
1.4 |
4.0 |
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* VILmin applied to each input pin, one at a time.
MOTOROLA |
3±118 |
MECL Data |
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DL122 Ð Rev 6 |
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