MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five D type latches with common reset and a common two±input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are ªORºed together.
Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. The reset input is enabled only when the clock is in the high state.
PD = 400 mW typ/pkg (No Load) tpd = 2.5 ns typ (Data to Output) tr, tf = 2.0 ns typ (20%±80%)
LOGIC DIAGRAM
D0 |
10 |
D |
Q |
14 |
Q0 |
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C |
R |
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D1 |
12 |
D |
Q |
15 |
Q1 |
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C |
R |
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D2 |
13 |
D |
Q |
2 |
Q2 |
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C |
R |
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D3 |
9 |
D |
Q |
3 |
Q3 |
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C |
R |
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D4 |
5 |
D |
Q |
4 |
Q4 |
C0 |
6 |
C |
R |
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VCC1 = PIN 1 |
C1 |
7 |
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VCC2 = PIN 16 |
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RESET |
11 |
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VEE = PIN 8 |
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MC10175
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q2 |
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2 |
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15 |
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Q1 |
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Q3 |
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3 |
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14 |
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Q0 |
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Q4 |
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4 |
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13 |
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D2 |
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D4 |
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5 |
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12 |
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D1 |
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RESET |
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C0 |
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6 |
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11 |
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D0 |
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C1 |
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7 |
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10 |
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VEE |
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8 |
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9 |
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D3 |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
TRUTH TABLE
D |
C0 |
C1 |
Reset |
Qn+1 |
L |
L |
L |
X |
L |
H |
L |
L |
X |
H |
X |
H |
X |
L |
Q n |
X |
X |
H |
L |
Q n |
X |
H |
X |
H |
L |
X |
X |
H |
H |
L |
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3/93
Motorola, Inc. 1996 |
3±126 |
REV 5 |
MC10175
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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107 |
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78 |
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97 |
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107 |
mAdc |
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Input Current |
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IinH |
6 |
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460 |
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290 |
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290 |
μAdc |
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7 |
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460 |
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290 |
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290 |
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10 |
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460 |
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290 |
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290 |
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11 |
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1000 |
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650 |
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650 |
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IinL |
All |
0.5 |
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0.5 |
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0.3 |
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μAdc |
Output Voltage |
Logic 1 |
VOH |
14 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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15 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
Logic 0 |
VOL |
14 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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15 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
14 |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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15 |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
14 |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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15 |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
(50Ω Load) |
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ns |
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Data Input |
t10+14+ |
14 |
1.0 |
3.6 |
1.0 |
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3.5 |
1.0 |
3.6 |
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t10±14± |
14 |
1.0 |
3.6 |
1.0 |
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3.5 |
1.0 |
3.6 |
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Clock Input |
t6±14+ |
14 |
1.0 |
4.7 |
1.0 |
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4.3 |
1.0 |
4.4 |
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t6±14± |
14 |
1.0 |
4.7 |
1.0 |
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4.3 |
1.0 |
4.4 |
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Reset Input |
t11+4± |
4 |
1.0 |
4.0 |
1.0 |
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3.9 |
1.0 |
4.2 |
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t11+14± |
14 |
1.0 |
4.0 |
1.0 |
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3.9 |
1.0 |
4.2 |
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Setup TIme |
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tsetup |
14 |
2.5 |
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2.5 |
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2.5 |
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Hold Time |
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thold |
14 |
1.5 |
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1.5 |
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1.5 |
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Rise Time |
(20 to 80%) |
t+ |
14 |
1.0 |
3.6 |
1.1 |
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3.5 |
1.1 |
3.7 |
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Fall Time |
(20 to 80%) |
t± |
14 |
1.0 |
3.6 |
1.1 |
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3.5 |
1.1 |
3.7 |
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1.Individually test each input; apply VILmin to pin under test.
2.Output latched to high logic state prior to test.
MECL Data |
3±127 |
MOTOROLA |
DL122 Ð Rev 6 |
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