MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4 Bit |
Serial/Parallel |
Converter |
|
MC10E445 |
|
|
|
|
|
The MC10/100E445 is an integrated 4-bit serial to parallel data |
|
MC100E445 |
||
|
|
|||
converter. The device is designed to operate for NRZ data rates of up to |
|
|
||
2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both |
|
|
||
4-bit conversion and a two chip 8-bit conversion function. The conversion |
|
|
||
sequence was chosen to convert the first serial bit to Q0, the second to |
|
|||
Q1 etc. |
|
|
|
|
• On-Chip Clock 4 and 8 |
|
|
4-BIT SERIAL/ |
|
• 2.0Gb/s Data Rate Capability |
|
|
||
|
|
PARALLEL CONVERTER |
||
• Differential Clock and Serial Inputs |
|
|
||
|
|
|
||
• VBB Output for Single-Ended Input Applications |
|
|
|
|
• Asynchronous Data Synchronization |
|
|
|
|
• Mode Select to Expand to 8-Bits |
|
|
|
|
|
|
|
||
• Internal 75kΩ Input Pulldown Resistors |
|
|
|
|
• Extended 100E VEE Range of ±4.2V to ±5.46V |
|
|
|
|
Two selectable serial inputs provide a loopback capability for testing |
|
|
||
purposes when the device is used in conjunction with the E446 parallel to |
|
|
||
serial converter. |
|
|
|
|
The start bit for conversion can be moved using the SYNC input. A |
|
FN SUFFIX |
||
single pulse applied asynchronously for at least two input clock cycles |
|
|||
shifts the start bit for conversion from Qn to Qn±1. For each additional |
|
PLASTIC PACKAGE |
||
shift required an additional pulse must be applied to the SYNC input. |
|
CASE 776-02 |
||
|
|
|||
Asserting the SYNC input will force the internal clock dividers to ªswallowº |
|
|
||
a clock pulse, effectively shifting a bit from the Qn to the Qn±1 output (see |
|
|
||
Timing Diagram B). |
|
|
|
|
The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E445's. When cascaded in an 8-bit conversion scheme the devices will not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential input and bypassed via a 0.01μF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design guide in the ECLinPS data book.
Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E445's in a system the master reset must be asserted.
PIN NAMES
Pin |
Function |
||
|
|
|
|
SINA, SINA |
Differential Serial Data Input A |
||
SINB, SINB |
Differential Serial Data Input B |
||
SEL |
Serial Input Selector Pin |
||
Q0±Q3 |
Parallel Data Outputs |
||
|
|
|
|
CLK, CLK |
Differential Clock Inputs |
||
CL/4, CL/4 |
Differential 4 Clock Output |
||
CL/8, CL/8 |
Differential 8 Clock Output |
||
MODE |
Conversion Mode 4-Bit/8-Bit |
||
SYNCH |
Conversion Synchronizing Input |
||
|
|
|
|
FUNCTION TABLES
|
Mode |
|
Conversion |
SEL |
Serial Input |
|
|
|
|
|
|
|
L |
|
4-Bit |
H |
A |
|
H |
|
8-Bit |
L |
B |
|
|
|
|
|
|
8/97 |
|
|
|
|
|
Motorola, Inc. 1997 |
|
1 |
|
||
|
|
|
|
|
|
|
SYNC |
RESET |
|
|
|
||
|
|
|
SINA SINA |
MODE NC VCCO |
|
||||||||
SINB |
26 |
|
|
|
24 |
23 |
22 |
21 |
20 |
19 |
SOUT |
||
25 |
|
||||||||||||
|
|
|
|
|
|
|
|
|
18 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
17 |
|
SINB |
27 |
|
|
|
|
|
|
|
|
|
SOUT |
||
|
SEL |
28 |
|
|
|
|
|
|
|
|
|
16 |
VCC |
V |
1 |
|
Figure 1. 28±Lead Pinout |
15 |
Q0 |
||||||||
|
EE |
|
|
|
|
|
(Top View) |
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
||||
|
CLK |
2 |
|
|
|
|
|
|
|
|
|
14 |
Q1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLK |
3 |
|
|
|
|
|
|
|
|
|
13 |
VCCO |
VBB |
4 |
|
|
|
|
|
|
|
|
|
12 |
Q2 |
|
|
|
|
5 |
|
6 |
7 |
8 |
9 |
10 |
11 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
CL/8 |
CL/8 VCCO CL/4 |
CL/4 VCCO |
Q3 |
|
||||||
REV 3
MC10E445 MC100E445
SINB |
|
|
|
|
|
|
|
|
SINB |
|
|
|
D |
Q |
D |
Q |
Q3 |
SINA |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
SINA |
|
|
|
|
|
|
|
|
SEL |
|
|
|
|
|
|
|
|
|
|
|
|
D |
Q |
D |
Q |
Q2 |
|
|
|
|
D |
Q |
D |
Q |
Q1 |
|
|
|
|
D |
Q |
D |
Q |
Q0 |
|
|
|
|
|
|
|
|
SOUT |
|
|
|
|
|
|
|
|
SOUT |
|
|
|
|
|
|
0 |
|
|
|
|
|
|
|
|
1 |
|
|
MODE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Out |
|
CL/4 |
|
|
|
|
|
|
|
CL/4 |
|
CLK |
|
|
|
|
|
4 |
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
CLK |
|
|
In |
Out |
|
R |
|
|
|
|
|
|
|
|
|
||
|
|
Latch |
|
|
|
|
||
|
|
|
|
|
|
|
||
|
|
|
|
EN |
|
|
|
|
|
|
|
|
|
|
Out |
|
CL/8 |
|
|
|
|
|
|
|
CL/8 |
|
|
|
|
|
|
|
2 |
|
|
|
|
|
|
|
|
|
|
|
SYNC |
D |
Q |
D |
|
|
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Q |
|
|
|
|
|
RESET |
|
|
|
|
|
|
|
|
Figure 2. Logic Diagram
MOTOROLA |
2 |
ECLinPS and ECLinPS Lite |
|
|
DL140 Ð Rev 4 |
MC10E445 MC100E445
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
|
|
|
0°C |
|
|
25°C |
|
|
85°C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Symbol |
Characteristic |
Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
Condition |
|
|
|
|
|
|
|
|
|
|
|
|
|
IIH |
Input HIGH Current |
|
|
150 |
|
|
150 |
|
|
150 |
μA |
|
VOH |
Ouput HIGH Current |
±1020 |
|
±790 |
±980 |
|
±760 |
±910 |
|
±670 |
V |
1 |
|
10E (SOUT Only) |
|
|
|
|
|||||||
|
100E (SOUT Only) |
±1025 |
|
±830 |
±1025 |
|
±830 |
±1025 |
|
±830 |
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
VBB |
Output Reference Voltage |
±1.38 |
|
±1.27 |
±1.35 |
|
±1.25 |
±1.31 |
|
±1.19 |
V |
|
|
10E |
|
|
|
|
|
||||||
|
100E |
±1.38 |
|
±1.26 |
±1.38 |
|
±1.26 |
±1.38 |
|
±1.26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IEE |
Power Supply Current |
|
154 |
185 |
|
154 |
185 |
|
154 |
185 |
mA |
|
|
10E |
|
|
|
|
|
||||||
|
100E |
|
154 |
185 |
|
154 |
185 |
|
177 |
212 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels.
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
|
|
|
0°C |
|
|
25°C |
|
|
85°C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Symbol |
Characteristic |
Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
Condition |
|
|
|
|
|
|
|
|
|
|
|
|
|
fMAX |
Maximum Conversion Frequency |
2.0 |
|
|
2.0 |
|
|
2.0 |
|
|
Gb/s |
|
|
|
|
|
|
|
|
|
|
|
|
NRZ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tPLH |
Propagation Delay to Output |
|
|
|
|
|
|
|
|
|
ps |
|
tPHL |
CLK to Q |
1500 |
1800 |
2100 |
1500 |
1800 |
2100 |
1500 |
1800 |
2100 |
|
|
|
CLK to SOUT |
800 |
975 |
1150 |
800 |
975 |
1150 |
800 |
975 |
1150 |
|
|
|
CLK to CL/4 |
1100 |
1325 |
1550 |
1100 |
1325 |
1550 |
1100 |
1325 |
1550 |
|
|
|
CLK to CL/8 |
1100 |
1325 |
1550 |
1100 |
1325 |
1550 |
1100 |
1325 |
1550 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ts |
Setup Time |
±100 |
±250 |
|
±100 |
±250 |
|
±100 |
±250 |
|
ps |
|
|
SINA, SINB |
|
|
|
|
|
||||||
|
SEL |
0 |
±200 |
|
0 |
±200 |
|
0 |
±200 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
th |
Hold Time |
450 |
300 |
|
450 |
300 |
|
450 |
300 |
|
ps |
|
|
SINA, SINB, SEL |
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
tRR |
Reset Recovery Time |
500 |
300 |
|
500 |
300 |
|
500 |
300 |
|
ps |
|
tPW |
Minimum Pulse Width |
400 |
|
|
400 |
|
|
400 |
|
|
ps |
|
|
CLK, MR |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
tr |
Rise/Fall Times |
|
|
|
|
|
|
|
|
|
ps |
20%±80% |
tf |
SOUT |
100 |
225 |
350 |
100 |
225 |
350 |
100 |
225 |
350 |
|
|
|
Other |
200 |
425 |
650 |
200 |
425 |
650 |
200 |
425 |
650 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECLinPS and ECLinPS Lite |
3 |
MOTOROLA |
DL140 Ð Rev 4
Loading...