MC10E142
D
2
D
3
D
4
V
CCO
Q
0
Q
1
Q
2
V
CCO
D
5
D
6
D
7
D
8
SEL
MR
CLK1
CLK2
V
EE
S-IN
D
0
D
1
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
8
Q
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
1
LOGIC DIAGRAM
S-IN
D
0
D
1
D
2
D
3
D
8
SEL
CLK1
CLK2
MR
Q
0
Q
1
Q
2
Q
3
Q
8
D
Q
D
D
D
D
Q
Q
Q
Q
1
0
1
0
1
0
1
0
1
0
Pinout: 28-Lead PLCC
(Top View)
* All V
CC
and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity
applications in mind. The E142 performs serial/parallel in and
serial/parallel out, shifting in one direction. The nine inputs D0 – D8
accept parallel input data, while S-IN accepts serial input data. The Qn
outputs do not need to be terminated for the shift operation to function. T o
minimize noise and power, any Q output not used should be left
unterminated.
• 700MHz Min. Shift Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The SEL (Select) input pin is used to switch between the two modes of
operation — SHIFT and LOAD. The shift direction is from bit 0 to bit 8.
Input data is accepted by the registers a set-up time before the positive
going edge of CLK1 or CLK2; shifting is also accomplished on the positive
clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets
all the resisters to zero.
PIN NAMES
Pin Function
D
0
– D
8
Parallel Data Inputs
S-IN Serial Data Input
SEL Mode Select Input
CLK1, CLK2 Clock Inputs
MR Master Reset
Q
0
– Q
8
Data Outputs
FUNCTIONS
SEL Mode
L
H
Load
Shift
9-BIT SHIFT
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
查询MC100E142供应商
MC10E142 MC100E142
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (V
EE
= V
EE
(min) to V
EE
(max); V
CC
= V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 120 145 120 145 120 145
100E 120 145 120 145 138 165
AC CHARACTERISTICS (V
EE
= V
EE
(min) to V
EE
(max); V
CC
= V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
f
SHIFT
Max. Shift Frequency 700 900 700 900 700 900 MH
z
t
PLH
Propagation Delay to Output ps
t
PHL
Clk 600 800 1000 600 800 1000 600 800 1000
MR 600 800 1000 600 800 1000 600 800 1000
t
s
Setup Time ps
D 50 –100 50 –100 50 –100
SEL 300 150 300 150 300 150
t
h
Hold Time ps
D 300 100 300 100 300 100
SEL 75 –150 75 –150 75 –150
t
RR
Reset Recovery Time 900 700 900 700 900 700 ps
t
PW
Minimum Pulse Width ps
Clk, MR 400 400 400
t
SKEW
Within-Device Skew 75 75 75 ps Note 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 525 800 300 525 800 300 525 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
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