Motorola MC10212L, MC10212P, MC10212FN Datasheet

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Motorola MC10212L, MC10212P, MC10212FN Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

High Speed Dual 3-Input/

3-Output OR/NOR Gate

The MC10212 is designed to drive up to six transmission lines simul± taneously. The multiple outputs of this device also allow the wire ªORº±ing of several levels of gating for minimization of gate and package count.

The ability to control three parallel lines with minimum propagation delay from a single point makes the MC10212 particularly useful in clock distribution applications where minimum clock skew is desired.

PD = 160 mW typ/pkg (No Load) tpd = 1.5 ns typ (All Outputs Loaded) tr, tf = 1.5 ns typ (20%±80%)

LOGIC DIAGRAM

4

3

5

6 2

7

12

13

9

10 14

11

VCC1 = PIN 1, 15

VCC2 = PIN 16

VEE = PIN 8

MC10212

L SUFFIX

CERAMIC PACKAGE

CASE 620±10

P SUFFIX

PLASTIC PACKAGE

CASE 648±08

FN SUFFIX

PLCC

CASE 775±02

DIP

PIN ASSIGNMENT

VCC1

 

1

 

16

 

 

VCC2

 

 

 

 

AOUT

 

2

 

15

 

 

VCC1

 

 

 

 

 

 

 

 

 

 

 

 

BOUT

AOUT

 

3

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AOUT

 

4

 

13

 

 

BOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

AIN

 

5

 

12

 

 

BOUT

 

 

 

 

AIN

 

6

 

11

 

 

BIN

 

 

 

 

AIN

 

7

 

10

 

 

BIN

 

 

 

 

VEE

 

8

 

9

 

 

BIN

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).

3/93

Motorola, Inc. 1996

3±192

REV 5

MC10212

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

Test Limits

 

 

 

 

 

 

 

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

±30°C

 

 

+25°C

 

+85°C

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristic

Symbol

Test

Min

Max

Min

 

Typ

 

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Drain Current

IE

8

 

42

 

 

30

 

38

 

42

mAdc

Input Current

 

IinH

5, 6, 7

 

650

 

 

 

 

410

 

410

μAdc

 

 

IinL

5, 6, 7

0.5

 

0.5

 

 

 

 

0.3

 

μAdc

Output Voltage

Logic 1

VOH

2

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

Vdc

 

 

 

3

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

4

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage

Logic 0

VOL

2

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

Vdc

 

 

 

3

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

4

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 1

VOHA

2

±1.080

 

±0.980

 

 

 

 

±0.910

 

Vdc

 

 

 

3

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

4

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 0

VOLA

2

 

±1.655

 

 

 

 

±1.630

 

±1.595

Vdc

 

 

 

3

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

4

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Times

(50Ω Load)

 

 

 

 

 

 

 

 

 

 

 

ns

Propagation Delay

t5+2+

2

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t5±2±

2

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t5+3±

3

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t5±3+

3

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t5+4±

4

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t5±4+

4

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

Rise Time

(20 to 80%)

t2+

2

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t3+

3

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t4+

4

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

Fall Time

(20 to 80%)

t

2

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t

3

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

 

 

t

4

1.0

2.6

1.0

 

1.5

 

2.5

1.0

2.8

 

MECL Data

3±193

MOTOROLA

DL122 Ð Rev 6

 

 

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