Motorola MC100LVEL39DW, MC100LVEL39DWR2, MC100EL39, MC100EL39DW, MC100EL39DWR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2/4, 4/6 Clock

Generation Chip

The MC100LVEL39 is a low skew 2/4, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL39 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple LVEL39s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device.

•50ps Output-to-Output Skew

•Synchronous Enable/Disable

•Master Reset for Synchronization

•75kΩ Internal Input Pulldown Resistors

•>2000V ESD Protection

•Low Voltage VEE Range of ±3.0 to ±3.8V

Pinout: 20-Lead SOIC (Top View)

	VCC		Q0		Q0		Q1		Q1		Q2		Q2		Q3		Q3		VEE
	20		19		18		17		16		15		14		13		12		11

	1			2			3		4		5		6		7		8		9		10
	VCC			EN		DIVSELb CLK					CLK		VBB		MR		VCC		NC DIVSELa

MC100LVEL39

MC100EL39

1

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

			PIN DESCRIPTION
	PIN				FUNCTION
	CLK				Diff Clock Inputs
	EN				Sync Enable
	MR				Master Reset
	VBB				Reference Output
	Q0, Q1				Diff 2/4 Outputs
	Q2, Q3				Diff 4/6 Outputs
	DIVSEL				Frequency Select Input
			FUNCTION TABLE
	CLK		EN			MR		FUNCTION
	Z		L			L		Divide
	ZZ		H			L		Hold Q0±3
	X		X			H		Reset Q0±3
	Z = Low-to-High Transition
	ZZ = High-to-Low Transition
	DIVSELa				Q0, Q1 OUTPUTS
	0				Divide by 2
	1				Divide by 4
	DIVSELb				Q2, Q3 OUTPUTS
	0				Divide by 4
	1				Divide by 6

3/96

Motorola, Inc. 1996

REV 2

MC100LVEL39 MC100EL39

		LOGIC DIAGRAM
	DIVSELa
		Q0
	CLK	2/4
		Q0
	CLK	R
		Q1
		Q1
	EN	Q2
		4/6
		Q2
		R
		Q3
	MR	Q3
	DIVSELb

CLK

Q ( 2)

Q ( 4)

Q ( 6)

Figure 1. Timing Diagrams

MC100LVEL39

DC CHARACTERISTICS (VEE = ±3.8V to ±3.0; VCC = GND)

±40°C

0°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

50

59

50

59

50

59

54

61

mA

VBB

Output Reference Voltage

±1.38

±1.26

±1.38

±1.26

±1.38

±1.26

±1.38

±1.26

V

IIH

Input High Current

150

150

150

150

mA

MC100LVEL39

AC CHARACTERISTICS (VEE = ±3.8V to ±3.0; VCC = GND)

				±40°C			0°C			25°C			85°C
Symbol	Characteristic		Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
fMAX	Maximum Toggle Frequency		1000			1000			1000			1000			MHz
tPLH	Propagation Delay	CLK → Q (Diff)	760		960	780		980	800		1000	850		1050	ps
tPHL	to Output	CLK → Q (S.E.)	710		1010	730		1030	750		1050	800		1100
		MR → Q	600		900	600		900	610		910	630		930
tSKEW	Within-Device Skew1	Q0 ± Q3			50			50			50			50	ps
	Part-to-Part	Q0 ± Q3 (Diff)			200			200			200			200
tS	Setup Time	EN → CLK	250			250			250			250			ps
		DIVSEL → CLK	400			400			400			400
tH	Hold Time	CLK → EN	100			100			100			100			ps
		CLK → Div_Sel	150			150			150			150

MOTOROLA

4±2